Instantiating Multiple modules and making connections in Chisel

[jayan...@gmail.com]

Hi
I have a Switch with 8 inputs and a  Mux with 7 inputs. The concept is that is Switch output will be from one of the remaining 7 inputs of the Switch and for that the Mux is required to be only 7 to 1 if the switch has 8 inputs.

I have created the Switch using the following Chisel code

class Switch[T <: Data] ( gen: T, ports : Int, widthParam : Int, nConfig: Int) extends Module{
   
    val io    = new Bundle{
        val inPort = Vec.fill(ports){gen.clone.asInput}
        val outPort = Vec.fill(ports){gen.clone.asOutput}    
        }

For designing the Mux I have used the following code

class MuxSwitch[T <: Data] (gen : T, ports: Int, widthParam : Int) extends Module{
    val io    = new Bundle{
        val inMuxPort    = Vec.fill(ports){gen.clone.asInput}
        val sel    = UInt(INPUT, width = log2Up(ports))
        val outMuxPort    = UInt(OUTPUT, width = widthParam)
        }
       
        io.outMuxPort := io.inMuxPort(io.sel)
}

Now for instantiating the same mux multiple times, as many times as the outputs of the Switch, which are 8 in this case , I am using two approaches.

Fist approach

val mux = Vec.fill(ports){Module(new MuxSwitch[UInt](UInt(width=widthParam),(ports-1), widthParam)).io}

Second approach

for(i<- 0 until ports)
    {    
        val mux = Chisel.Module (
            new MuxSwitch[UInt](UInt(width=widthParam),(ports-1), widthParam)
        )
}

The problem I am facing is in making the interconnections of the input ports inMuxPort to inPort of the switch. Mind it that the Switch has one less input port as compared to the input ports of the switch so I have to skip one port while making interconnections. But for the purpose I am not able to find any appropriate method and also I am not sure which of the above methods will work better for me while instantiaing the Mux modules.

[Stephen Tridgell]

You need to maintain a reference to the modules you created. Why not

val muxAry = (0 until ports).map(x=>  {  Module(new  MuxSwitch[UInt](UInt(width=widthParam, ports - 1, widthParam)}).toList
muxAry[0].io.inPort  // ... etc

[jayan...@gmail.com]

Hi
I am still not bale to understand it. Can you elaborate it a little bit. I am actually new to Chisel.

[Stephen Tridgell]

The important thing to remember in chisel is that you are programming in chisel and scala. This means you can use scala data structures (like List) to help you descibe hardware.

Consider the following to instantiate multiple times:

val inst0 = Module(new FooBar(args))
val inst1 = Module(new FooBar(args))
val inst2 = Module(new FooBar(args))
val inst3 = Module(new FooBar(args))
val inst4 = Module(new FooBar(args))
val inst5 = Module(new FooBar(args))

This would work for what you wanted but is terrible coding style for many reasons. To make it slightly better we could do this:

val listInst=List(inst0, inst1,...)

which allows us to access inst0 via:

listInst(0).io//etc...

Scala has a nice function called map which we can use in situations like this.

(0 until ports)  // generates a list of numbers
(0 until ports).map(x => Module(new FooBar(args))) // for each number in that list, transform it into inst0, inst1, ... etc
(0 until ports).map(x => Module(new FooBar(args))).toList // just ensure its a list, i find this makes it more readable too
val muxAry = (0 until ports).map(x => Module(new FooBar(args))).toList // store the list in muxAry
muxAry(0).io.out := muxAry(1).io.in // use it however you want

Makes sense?

[jayan...@gmail.com]

Yes it does make sense now. Thanks