Chisel 5.0.0: Provider firrtl.passes.memlib.MemLibOptions not found

[Madhava Krishna]

It trying the diplomatic adder in Chisel 5.0.0 with rocket-chip as a library.

I'm able to print verilog using the code below.

"""
  val verilog = ChiselStage.emitSystemVerilog(
    LazyModule(new AdderTestHarness()(Parameters.empty)).module
  )
  println(s"```verilog\n$verilog```")

"""

but when using emitSystemVerilogFile as shown below,

"""

ChiselStage.emitSystemVerilogFile(
    LazyModule(new AdderTestHarness()(Parameters.empty)).module
 )
 """
the compilation fails with below error.

========================

Exception in thread "main" java.util.ServiceConfigurationError: firrtl.options.RegisteredLibrary: Provider firrtl.passes.memlib.MemLibOptions not found
at java.base/java.util.ServiceLoader.fail(ServiceLoader.java:589)
at java.base/java.util.ServiceLoader$LazyClassPathLookupIterator.nextProviderClass(ServiceLoader.java:1212)
at java.base/java.util.ServiceLoader$LazyClassPathLookupIterator.hasNextService(ServiceLoader.java:1221)
at java.base/java.util.ServiceLoader$LazyClassPathLookupIterator.hasNext(ServiceLoader.java:1265)
at java.base/java.util.ServiceLoader$2.hasNext(ServiceLoader.java:1300)
at java.base/java.util.ServiceLoader$3.hasNext(ServiceLoader.java:1385)
at firrtl.options.Shell.registeredLibraries$lzycompute(Shell.scala:52)
at firrtl.options.Shell.registeredLibraries(Shell.scala:49)
at firrtl.options.Shell.parserSetup(Shell.scala:63)
at firrtl.options.BareShell.parse(Shell.scala:33)
at firrtl.options.Stage.execute(Stage.scala:56)
at circt.stage.ChiselStage$.emitSystemVerilogFile(ChiselStage.scala:221)
at adder.diplomacyExample$.delayedEndpoint$adder$diplomacyExample$1(Top.scala:30)
at adder.diplomacyExample$delayedInit$body.apply(Top.scala:27)
at scala.Function0.apply$mcV$sp(Function0.scala:42)
at scala.Function0.apply$mcV$sp$(Function0.scala:42)
at scala.runtime.AbstractFunction0.apply$mcV$sp(AbstractFunction0.scala:17)
at scala.App.$anonfun$main$1(App.scala:98)
at scala.App.$anonfun$main$1$adapted(App.scala:98)
at scala.collection.IterableOnceOps.foreach(IterableOnce.scala:576)
at scala.collection.IterableOnceOps.foreach$(IterableOnce.scala:574)
at scala.collection.AbstractIterable.foreach(Iterable.scala:933)
at scala.App.main(App.scala:98)
at scala.App.main$(App.scala:96)
at adder.diplomacyExample$.main(Top.scala:27)

at adder.diplomacyExample.main(Top.scala)

I would appreciate any pointers to fix this.

Thanks.

[Ruige Lee]

I just deleted the code:  `firrtl.passes.memlib.MemLibOptions` in `rocket-chip/src/main/resources/META-INF/services/firrtl.options.RegisteredLibrary`. And it worked, but I did not know why.

[Madhava Krishna]

Thanks, deleting the file worked.

BTW, generating a .fir file using ChiselStage.emitCHIRRTL and then using firtool to spit verilog also works.

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