sv2chisel 0.5.0 release

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jjb vhc

Feb 17, 2022, 9:05:41 AM2/17/22
Dear Chisel community,

I am quite proud to announce the first proper release of sv2chisel, the automated (System)Verilog to Chisel translator!

> Overview of features and limitations <  including most notably:
- sv2chisel translation options
- sv2chisel-helpers introducing Chisel as IP integration utilities
All instructions to get started in the main README (spoiler: it's quite easy)


Versioning is aligned on chisel stack version policy and this release is fully compatible with chisel stack x.5.+ (hence this initial release at x.5)
- sv2chisel generates valid chisel3 3.5.+
- sv2chisel-helpers is published with a dependency on chisel3 3.5.0, de facto compatible with all chisel3 3.5.+ versions


I really hope this will be useful to all Chisel-enthusiasts, both to translate existing HDL sources and integrate Chisel as IP into larger projects : do not hesitate to spread the word to all hardware engineers !


Jean (John) Bruant
PhD student at OVHcloud in partnership with TIMA lab
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