How do I register all inputs and outputs of a module?

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Øyvind Harboe

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Sep 29, 2023, 11:25:03 AM9/29/23
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I want to use OpenROAD and ASAP7 to measure the setup time for a module.

To do so, I need for a Foo module to create a FooTop module where I register all inputs and outputs.

How can I best do this in Chisel?

I want to do something like:

class FooTop extends Bundle {
 val io = IO(new FooBundle)
 val bar = Module(new Foo) 
 val reg = Reg(new FooBundle)
 io <> reg
 bar.io <> reg
}





Error message: firrtl.passes.CheckHighFormLike$RegWithFlipException:  @[src/main/scala/main.scala 19:15]: [module FooTop] Register reg cannot be a bundle type with flips.


Schuyler Eldridge

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Oct 9, 2023, 3:49:50 PM10/9/23
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There are likely better ways of doing this than what I suggest below.

You can strip the type of the bundle to make it passive before creating the register. You then need to do per-field connections to the register.

E.g., something like the following will work:

```
class Foo extends Module {
  val a = IO(Flipped(new Bar))
  val b = IO(new Bar)

  val r = Reg(Output(chiselTypeOf(a)))

  r.x :<= a.x
  r.y :<= b.y

  b.x :<= r.x
  a.y :<= r.y
}
```

The better approach is that there is likely a pithy way to do this with either: (1) the new connection operators or (2) a utility. What you really want is a way to have the left-hand-side connect (in a flipped or aligned fashion) ignoring the type of the right-hand-side passive thing.

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Øyvind Harboe

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Oct 9, 2023, 5:29:55 PM10/9/23
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Where can I find documentation on these new operators. I have not seen the :<= operator....

Yes... it would be nice to have a pithy way to do this... :-)

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Schuyler Eldridge

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Oct 9, 2023, 5:30:59 PM10/9/23
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Øyvind Harboe

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Oct 10, 2023, 1:31:57 AM10/10/23
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Thanks!

What happened to the <> operator? Is this now written :<>= ?



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Øyvind Harboe
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Schuyler Eldridge

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Oct 10, 2023, 10:59:35 AM10/10/23
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The intent of the new connection operators is that you don't have to use the old ones anymore. For almost all situations, you will want to use `:<>=` and it will do what you want.

The original monoconnect `:=` and biconnect `<>` operators are still there and are rewritten using the new operators. These operators were kind of odd in that they were both, almost, doing the same thing (`:=` is bi-directional, just only for fields on the LHS and `<>` was bi-directional, but both the LHS and RHS needed to have the same fields). There's documentation on those in another section which gets into the exact semantics of these in more detail: https://www.chisel-lang.org/chisel3/docs/explanations/interfaces-and-connections.html#bulk-connections

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