Generate verilog file with different file name

[Chin Tsai]

Hello,

If I do

(new chisel3.stage.ChiselStage).emitVerilog(new Foo)

It generates a file called Foo.v

Is it possible to generate verilog file of a module with a name other than module's name?

Thanks

[Jack Koenig]

Hello,

You can use command-line argument -o. Since you're using class chisel3.stage.ChiselStage, I assume you're using Chisel 3.6.0 or older:

(new chisel3.stage.ChiselStage).emitVerilog(new Foo, Array("-o", "<outputfilename>.v"))

In Chisel 5.0 and newer, you use firtoolOpts (since firtool is doing the actual Verilog emission):

circt.stage.ChiselStage.emitSystemVerilogFile(new Foo, firtoolOpts = Array("-o", "<outputfilename>.v"))

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