Chisel v3.6.0-RC3 has been released!

[Jack Koenig]

Howdy Chiselers,

I am very delighted to announce that we have released v3.6.0-RC3 of the various Chisel-related projects:

Chisel v3.6.0-RC3 - https://github.com/chipsalliance/chisel3/releases/tag/v3.6.0-RC3

ChiselTest, Treadle, and FIRRTL also have 0.6.0-RC3 and 1.6.0-RC3 releases respectively, but with relatively minor changes.

The 3.6 release is a big step for the future of Chisel as it is the transitional release from the original Scala FIRRTL Compiler to the new LLVM MLIR-based FIRRTL Compiler. Please see the Chisel release notes linked above.

Please try out Chisel v3.6.0-RC3 to help us squash any bugs before the final v3.6.0 release! I expect to release v3.6.0 next week!

~Jack on behalf of the Chisel development team

P.S. My usual Scastie template now using 3.6.0-RC3: https://scastie.scala-lang.org/8Riy7YqEQ3yAOztcgcZPbA

[Øyvind Harboe]

I tried it: the SystemVerilog output from LLVM CIRCT is unchanged in my case.

The only thing I had to change was to modify MuxLookup(a, b, c) to MuxLookup(a, b)(c) to fix a deprecation warning.