Black-Box files cannot generate in one verilog files, when using chisel5

[Ruige Lee]

Hello, I am trying to bump from chisel 3.5.6 to chisel5.

However, when I try to generate all code in one verilog file. the black-box file is missing.

How can I resolve this? Here the code:

object testMain extends App {

  val cfg = new Rift2330

  (new circt.stage.ChiselStage).execute(

    Array(

      "--target-dir", "generated/Main",

      "--target", "verilog",

      // "--split-verilog",

      ) ++ args,

    Seq(

      chisel3.stage.ChiselGeneratorAnnotation( () => {

        val soc = LazyModule(new Rift2Chip()(cfg))

        soc.module

      }),

      circt.stage.FirtoolOption("--disable-annotation-unknown"),

      circt.stage.FirtoolOption( "--dedup"),

    )

  )

}

And the generated code end with:

// ----- 8< ----- FILE "firrtl_black_box_resource_files.f" ----- 8< -----

plusarg_reader.v

the file,`plusarg_reader.v`,did not merge in the file, but shows as a note!