Negative in wire indexes in Verilog, should I be worried?

[Rupert Smith]

I notice this in the generated Verilog:

  wire[-7:0] cs_3;

  wire[-7:0] cs_2;

  wire[-7:0] cs_1;

  wire[-7:0] cs_0;

Wired declared over a negative range of indexes. Is this Verilog ok? This was generated from this statement, which breaks a 32-bit integer down into its component bytes:

  val cs = Vec(Range(0, 4).map(i => io.in(i * 8, (i + 1) * 8 - 1)))

I'm curious as to why this ones gets mapped onto a negative range...

Rupert

[Jonathan Bachrach]

this should be caught by chisel.

i’ll file the bug.

meanwhile i think you should be reversing the arguments

  val cs = Vec(Range(0, 4).map(i => io.in((i + 1) * 8 - 1, i * 8)))

to have the high index first then the low index.

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[Rupert Smith]

On 1 November 2013 17:35, Jonathan Bachrach <jackba...@gmail.com> wrote:

meanwhile i think you should be reversing the arguments

  val cs = Vec(Range(0, 4).map(i => io.in((i + 1) * 8 - 1, i * 8)))

to have the high index first then the low index.

Yes, of course. Thanks.

Rupert