chisel-users

Thinking about it there could be a solution with trait `HasBlackBoxInline` ```Scala class TestVec

Hello, So, do you think it's possible to improve the performances of this test ? Or do I have to

Hi all, sorry for a bit of spamming here. The FPL conference is free of charge and there is a Chisel

Hi George, This is the list for the Chisel Hardware Construction Language (https://www.chisel-lang.

Hi, I wrote some projects for FPGA with Chisel, maybe it can be added to https://www.chisel-lang.org/

Thanks for reaching out! I have added Pillars to the community page. Please let me know if there are

Hi Wang-san, Thank you for your advice! I tried both of litValue() and litToBoolean, it makes an

Dear Chisel Users, Due to some speakers' reason, some meetings have been rescheduled, but won

Dear all, just a reminder that the Chisel Community Conference starts in a few hours. See https://www

> On Jun 15, 2021, at 04:12, Süleyman Savas <bmsuleymansavas@gmail.com> wrote: > > Hi,

Since Chisel does not support negedge so in our project we wrote a python script that replaces if(

You can do something like make a bundle of without flop and flop the comp bundle to assign to the

When developing titlelink based managers, it is necessary to know all Ids of masters mapped from

Chisel3-plugin is part of the release. It's part of the Chisel v3.4.3 release notes, but I'll

Perhaps a good thing to note in the release notes of Chisel 3.5? Thanks! On Friday, May 21, 2021 at 3

Awesome, thanks very much works like a charm :) On Fri, May 21, 2021 at 4:44 PM Hadir Khan <

I'm getting this error message in my Chisel tests after upgrading. I'm not sure how to track

Ooops... never mind... "chiseltest" -> "0.3-SNAPSHOT" should be: "

Thanks! We're using Visual Studio Code. Chisel is only one thing that we're working on, so we

I would like to dump some files into the test_run_folder in my test. Is there a way to get to the

Hello, everyone! The Chisel Community Conference China 2021 (CCC2021) is planned for June 25, 2021 at

Looks like this is well in hand... It is a matter of resources.... Thanks for the clarifications! tir

The advantage of trimming the signals would be that the generated Verilog would be closer to hand-

This was very helpful. Thanks! I find that it is oftentimes easier and clearer to write Chisel code

Aha! I think about "instance name" as an identifier name. Scala uses identifier too, it

The Vec() in my case is used together with a Scala Enumeration. Also, I assign sequences to the Vec()

Good that you two are working on an update! The Chisel version is not so off from the current one, so

Thanks! I could copy and paste this into my code, but the real value comes when the code is more

This is long overdue, but there is now a page on the website documenting which versions work together

We have moved the repository, the new link is: https://github.com/chiselverify/documentation/tree/