chisel-users

Yes, that should be possible. Could you try to write up the example that is causing difficulties here

I don't have enough relevant experience to articulate such a PR in a reasonable amount of time...

Sorry, typo. That should have said that Chisel3 does NOT generate the C++ & emulator back-end

Hello I am trying to pipe-flush the Chisel front-end flow. Taken the existing ALU block and generated

Hi, I'd appreciate some pointers on how to add a static delay between interconnected diplomacy

Hi all, I know the Firrtl compiler does some optimizations such as constant folding and can generate

Howdy Chiselers, I am very delighted to announce that we have released v3.5.5 of the various Chisel-

Hi Edward, OK, great! Find attached what the current proposal for the tutorial is. We talked about a

You can use p"..." which still exists in Chisel 3.5.4 but existed in earlier versions as

Hi Shibo, sorry for the late answer. The FIFO is a generic one and needs a Chisel type to be passed (

Here you go: https://scastie.scala-lang.org/SIuMoax9RbiPnwcOAiurCA On Friday, October 28, 2022 at 2:

Hi Kevin, aah, I see. Thank you for your quick help! So I managed to do my formal “Hello World” :-)

asTypeOf(X) returns a new wire of type X, so this is working as intended. To complete the code you

My current solution is to have a helper class (in test, as this should not be in the main design part

Hi all, I have been trying to perform basic Floating Point Arithmetic operations. For starters, the

Dear all, O've update the Chisel book towards the 4th edition. Available as usual at: http://www.

I've modified my code so I no longer have these warnings. With the help of Jack, I found that

Hi, Very good, I look forward to the sessions. Please let us know when and where to look. Richard On

No actually, I want to do this.Any idea how can I do this: Actually, I have used the register. But

Shimomura Shigeki さんから Gmail 情報保護モードでメールが送信されました。 Re: Digest for chisel-users@googlegroups.com - 2

Dear all, I've published version 0.5.0 of ip-contributions. It is ready for Chisel 3.5. See:

Hello Chiselers, I am very delighted to announce that we have released v3.5.4 of the various Chisel-

Ah. Silly me :-) I was confused, all I was missing was to write: val a : UInt val b : UInt val c :

Hi Pinaki, I would recommend you start with the chisel template which can be found here: https://

Dear all, When I use a Vec as a combinational circuit (a mux) I need to wrap it into a Wire. When

Modules, which are Scala classes, are the tool to structure your circuit in modules/components. This

What I did when I needed gigabytes of memory for a design, is that I implement the memory in C++

That looks correct to me. Maybe a little bit surprising, but correct. Can you elaborate on why this

Another error I see: [info] firrtl.passes.CheckHighFormLike$UndeclaredReferenceException: @[FooUnit.

Hello Chiselers, I am very delighted to announce that we have released v3.5.3 of the various Chisel-