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AMIT RAJ
,
Martin Schoeberl
2
Jul 26
the below chisel code is a aeq module. when it get synthesize to verilog it has some problems in implementation on fpga.
Current FPGAs do not support two write ports. You need to change your code. Instead of having two
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the below chisel code is a aeq module. when it get synthesize to verilog it has some problems in implementation on fpga.
Current FPGAs do not support two write ports. You need to change your code. Instead of having two
Jul 26
Martoni
2
Jul 10
Where's all the explanation on the versions
So why the version 6.x is not the last chisel version ? Thanks Fabien M Le mercredi 26 juin 2024 à 09
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Where's all the explanation on the versions
So why the version 6.x is not the last chisel version ? Thanks Fabien M Le mercredi 26 juin 2024 à 09
Jul 10
家才崔
Jul 9
What categories of bugs do chisel users write most often?
Hello, wonderful members of the Chisel community! I hope you're all doing well. My name is Jacy
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What categories of bugs do chisel users write most often?
Hello, wonderful members of the Chisel community! I hope you're all doing well. My name is Jacy
Jul 9
Øyvind Harboe
6
Jul 7
Chisel 6.4.0 and new hierarchy API?
On Sunday, July 7, 2024 at 9:12:33 AM UTC+2 Øyvind Harboe wrote: Followup question. After discovering
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Chisel 6.4.0 and new hierarchy API?
On Sunday, July 7, 2024 at 9:12:33 AM UTC+2 Øyvind Harboe wrote: Followup question. After discovering
Jul 7
Martin Schoeberl
May 17
Final Call DSD conference (Chisel special session)
------------------------------------------------------------------------ DDVC: Digital Design and
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Final Call DSD conference (Chisel special session)
------------------------------------------------------------------------ DDVC: Digital Design and
May 17
Martin Schoeberl
May 15
Tiny Tapeout 07
Next chance for a Chisel based Tiny Tapeout. Start with the official template from https://github.com
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Tiny Tapeout 07
Next chance for a Chisel based Tiny Tapeout. Start with the official template from https://github.com
May 15
Martin Schoeberl
Apr 25
DSD Special Session on Chisel
Hi all, this is a gently reminder for a submission of a paper to the special session on Chisel at the
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DSD Special Session on Chisel
Hi all, this is a gently reminder for a submission of a paper to the special session on Chisel at the
Apr 25
Martin Schoeberl
Apr 22
DSD special session on Chisel
Dear all, this is a reminder to submit papers to the special session on Chisel at DSD 2024. See more
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DSD special session on Chisel
Dear all, this is a reminder to submit papers to the special session on Chisel at DSD 2024. See more
Apr 22
Nick Gian
Apr 16
Is chisel supporting blackbox for .systemVerilog?
Dear Community, Is chisel support .sv files as blackbox? if yes what version of chisel?.
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Is chisel supporting blackbox for .systemVerilog?
Dear Community, Is chisel support .sv files as blackbox? if yes what version of chisel?.
Apr 16
Martin Schoeberl
Apr 8
Chisel projects on Tiny Tapeout 06
Hi all, it is time for Chisel to get Tiny. A Chisel template is available, just in time, for Tiny
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Chisel projects on Tiny Tapeout 06
Hi all, it is time for Chisel to get Tiny. A Chisel template is available, just in time, for Tiny
Apr 8
Øyvind Harboe
Apr 2
BoringUtils.bore() is depricated, example of how to translate into modern speak?
Silly question: is there an example somewhere of how to switch BoringUtils.bore() deprecated syntax
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BoringUtils.bore() is depricated, example of how to translate into modern speak?
Silly question: is there an example somewhere of how to switch BoringUtils.bore() deprecated syntax
Apr 2
Nick Gian
Mar 27
Chisel 5 and blackbox an .SV
Can chisel (v5) handle blackbox as .sv files? because i only found examples with .v files
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Chisel 5 and blackbox an .SV
Can chisel (v5) handle blackbox as .sv files? because i only found examples with .v files
Mar 27
Øyvind Harboe
,
Øystein Hovind
3
Mar 6
Scala 3 and Chisel
Thanks! On Wednesday, March 6, 2024 at 10:28:57 AM UTC+1 oys...@ascenium.com wrote: Jack Koenig
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Scala 3 and Chisel
Thanks! On Wednesday, March 6, 2024 at 10:28:57 AM UTC+1 oys...@ascenium.com wrote: Jack Koenig
Mar 6
Nick Gian
,
Martoni
5
Feb 27
How to use floating point & fixed point
I have run the generating stuff but i want to run a chisel test in hardfloat. Can you help me how to
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How to use floating point & fixed point
I have run the generating stuff but i want to run a chisel test in hardfloat. Can you help me how to
Feb 27
Nick Gian
Feb 27
Can ChiselTest generate testbench verilog file?
Hello chisel community, Can chiselTest generate testbench verilog file? lf yes how?
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Can ChiselTest generate testbench verilog file?
Hello chisel community, Can chiselTest generate testbench verilog file? lf yes how?
Feb 27
Nick Gian
Feb 12
I want to compile and use FixedPoint & hardFloat for every project
I am using Chisel 3.6 and i want to use those 2 https://github.com/ucb-bar/fixedpoint/tree/chisel6?
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I want to compile and use FixedPoint & hardFloat for every project
I am using Chisel 3.6 and i want to use those 2 https://github.com/ucb-bar/fixedpoint/tree/chisel6?
Feb 12
qwer trump (zsjj)
, …
Dmitry Belimov
4
Feb 4
chiseltest failed on chisel 6.0
Hi All, Is it possible to transform Chisel code to C++ sources without iverilator? Why I ask this
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chiseltest failed on chisel 6.0
Hi All, Is it possible to transform Chisel code to C++ sources without iverilator? Why I ask this
Feb 4
chiselStudent
Jan 23
verilog output with Chisel v5.1.0
I am using the chisel-template gcd module and see that I can generate a system verilog file. using:
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verilog output with Chisel v5.1.0
I am using the chisel-template gcd module and see that I can generate a system verilog file. using:
Jan 23
Martin Schoeberl
Jan 23
bit order on asUInt
Hi all, I am wondering why the mapping of a Vec to UInt is different from mapping a Bundle: val vec =
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bit order on asUInt
Hi all, I am wondering why the mapping of a Vec to UInt is different from mapping a Bundle: val vec =
Jan 23
Ruige Lee
Jan 22
Black-Box files cannot generate in one verilog files, when using chisel5
Hello, I am trying to bump from chisel 3.5.6 to chisel5. However, when I try to generate all code in
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Black-Box files cannot generate in one verilog files, when using chisel5
Hello, I am trying to bump from chisel 3.5.6 to chisel5. However, when I try to generate all code in
Jan 22
Madhava Krishna
,
Ruige Lee
3
Jan 22
Chisel 5.0.0: Provider firrtl.passes.memlib.MemLibOptions not found
Thanks, deleting the file worked. BTW, generating a .fir file using ChiselStage.emitCHIRRTL and then
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Chisel 5.0.0: Provider firrtl.passes.memlib.MemLibOptions not found
Thanks, deleting the file worked. BTW, generating a .fir file using ChiselStage.emitCHIRRTL and then
Jan 22
Saltuk Akgül
Jan 3
Naming of modules
Hi everyone, I want to fix names of my modules. Not instance names but module names and generated
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Naming of modules
Hi everyone, I want to fix names of my modules. Not instance names but module names and generated
Jan 3
Martin Schoeberl
,
Schuyler Eldridge
7
12/11/23
Chisel 3.6
OK, that compiled. Thanks, Martin On 11.12.2023, at 17:46, Schuyler Eldridge <schuyler.eldridge@
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Chisel 3.6
OK, that compiled. Thanks, Martin On 11.12.2023, at 17:46, Schuyler Eldridge <schuyler.eldridge@
12/11/23
Gemma Tuner
12/7/23
Xforce Keygen 64-bit Inventor 2010 Keygen
Xforce Keygen 64-bit Inventor 2010 Keygen Download https://urlca.com/2wJ2Sf eebf2c3492
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Xforce Keygen 64-bit Inventor 2010 Keygen
Xforce Keygen 64-bit Inventor 2010 Keygen Download https://urlca.com/2wJ2Sf eebf2c3492
12/7/23
Arsh G
12/7/23
Re: Digest for chisel-users@googlegroups.com - 3 updates in 1 topic
Thanks to both of you :)) The help was much appreciated. On Tue, 5 Dec 2023 at 19:17, <chisel-
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Re: Digest for chisel-users@googlegroups.com - 3 updates in 1 topic
Thanks to both of you :)) The help was much appreciated. On Tue, 5 Dec 2023 at 19:17, <chisel-
12/7/23
Ina Tankesly
12/6/23
Nee Manasu Naaku Telusu [2003 €? FLAC]
Nee Manasu Naaku Telusu [2003 FLAC] Download File https://t.co/mZoAiKB8Xb eebf2c3492
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Nee Manasu Naaku Telusu [2003 €? FLAC]
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12/6/23
Ina Tankesly
12/6/23
Bhoothnath Returns Movie All Songs Download
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12/6/23
Ina Tankesly
12/6/23
Rizzato Nunes Direito Do Consumidor Pdf Download
Já a boa-fé objetiva, que é a que está presente no CDC,pode ser definida, grosso modo, como uma regra
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Rizzato Nunes Direito Do Consumidor Pdf Download
Já a boa-fé objetiva, que é a que está presente no CDC,pode ser definida, grosso modo, como uma regra
12/6/23
Ina Tankesly
12/6/23
Cf Auto Root Apk Download Now V1.1 (updated)
Rooting gives access to the advantages of installing updates, improving overall speed and battery
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Cf Auto Root Apk Download Now V1.1 (updated)
Rooting gives access to the advantages of installing updates, improving overall speed and battery
12/6/23
Ina Tankesly
12/6/23
ESET NOD32 ANTIVIRUS 2019 Crack License Key Full [Latest]
ESET NOD32 ANTIVIRUS 2019 Crack License Key Full [Latest] Download Zip https://t.co/1tqDr2FgWz
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12/6/23