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Feb 14

convert *.fir file to verilog

Hi, everyone. Recently I want to update rocket-chip version tracked by vivado-risc-v repo. In its

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convert *.fir file to verilog

Hi, everyone. Recently I want to update rocket-chip version tracked by vivado-risc-v repo. In its

Feb 14

Warren Savage, Edward Wang3

Feb 10

Test package names

Hi Edward, thank you. That explains it! Warren On Saturday, February 8, 2025 at 4:57:50 PM UTC-8

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Test package names

Hi Edward, thank you. That explains it! Warren On Saturday, February 8, 2025 at 4:57:50 PM UTC-8

Feb 10

Martin Schoeberl, Dmitry Belimov2

Feb 5

Chisel Book 6th edition

Dear Martin, Awesome, thank you very much! Best wishes ср, 5 февр. 2025 г. в 17:55, Martin Schoeberl

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Chisel Book 6th edition

Dear Martin, Awesome, thank you very much! Best wishes ср, 5 февр. 2025 г. в 17:55, Martin Schoeberl

Feb 5

Jan 14

LATTE Workshop Co-Located with ASPLOS 2025: Call for Papers

Hello Chiselers, I'm co-organising a workshop where Chisel-related work would be very welcomed!

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LATTE Workshop Co-Located with ASPLOS 2025: Call for Papers

Hello Chiselers, I'm co-organising a workshop where Chisel-related work would be very welcomed!

Jan 14

Vincent, Edward Wang4

11/21/24

Best way to check if an element is contained in a circular buffer?

Hi Vincent, You could consider something like this to ensure that the particular index is currently

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Best way to check if an element is contained in a circular buffer?

Hi Vincent, You could consider something like this to ensure that the particular index is currently

11/21/24

Martin Schoeberl

11/5/24

Tiny Tapeout 09

Hi all, Tiny Tapout run 09 is closing in a few days. However, it is still time to get your Chisel

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Tiny Tapeout 09

Hi all, Tiny Tapout run 09 is closing in a few days. However, it is still time to get your Chisel

11/5/24

11/1/24

VCD dumping in vanilla Chisel 6.5

In case anyone else was struggling with getting VCD dumps from the current svsim-style testing in the

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VCD dumping in vanilla Chisel 6.5

In case anyone else was struggling with getting VCD dumps from the current svsim-style testing in the

11/1/24

Martin Schoeberl2

10/31/24

publishing ip-contributions

Answering my own question: The format is the same as it was with uid/pwd: credentials += Credentials(

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publishing ip-contributions

Answering my own question: The format is the same as it was with uid/pwd: credentials += Credentials(

10/31/24

Martin Schoeberl

9/24/24

Fwd: [eecs-announce] Talk by Scott Beamer (UCSC) at SLICE Lab on Wed., 9/25/24 at 11:05 A.M., Room 380 Soda

Dear all, if you are in the Berkeley area this talk might interest you. Scott was involved in Chisel

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Fwd: [eecs-announce] Talk by Scott Beamer (UCSC) at SLICE Lab on Wed., 9/25/24 at 11:05 A.M., Room 380 Soda

Dear all, if you are in the Berkeley area this talk might interest you. Scott was involved in Chisel

9/24/24

8/1/24

Basic typecast error in chisel

{type mismatch; found : chisel3.UInt required: Int } at coloumnselectcounter. this error comes when i

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Basic typecast error in chisel

{type mismatch; found : chisel3.UInt required: Int } at coloumnselectcounter. this error comes when i

8/1/24

AMIT RAJ, Martin Schoeberl2

7/26/24

the below chisel code is a aeq module. when it get synthesize to verilog it has some problems in implementation on fpga.

Current FPGAs do not support two write ports. You need to change your code. Instead of having two

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the below chisel code is a aeq module. when it get synthesize to verilog it has some problems in implementation on fpga.

Current FPGAs do not support two write ports. You need to change your code. Instead of having two

7/26/24

7/10/24

Where's all the explanation on the versions

So why the version 6.x is not the last chisel version ? Thanks Fabien M Le mercredi 26 juin 2024 à 09

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Where's all the explanation on the versions

So why the version 6.x is not the last chisel version ? Thanks Fabien M Le mercredi 26 juin 2024 à 09

7/10/24

7/9/24

What categories of bugs do chisel users write most often?

Hello, wonderful members of the Chisel community! I hope you're all doing well. My name is Jacy

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What categories of bugs do chisel users write most often?

Hello, wonderful members of the Chisel community! I hope you're all doing well. My name is Jacy

7/9/24

Øyvind Harboe6

7/7/24

Chisel 6.4.0 and new hierarchy API?

On Sunday, July 7, 2024 at 9:12:33 AM UTC+2 Øyvind Harboe wrote: Followup question. After discovering

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Chisel 6.4.0 and new hierarchy API?

On Sunday, July 7, 2024 at 9:12:33 AM UTC+2 Øyvind Harboe wrote: Followup question. After discovering

7/7/24

Martin Schoeberl

5/17/24

Final Call DSD conference (Chisel special session)

------------------------------------------------------------------------ DDVC: Digital Design and

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Final Call DSD conference (Chisel special session)

------------------------------------------------------------------------ DDVC: Digital Design and

5/17/24

Martin Schoeberl

5/15/24

Tiny Tapeout 07

Next chance for a Chisel based Tiny Tapeout. Start with the official template from https://github.com

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Tiny Tapeout 07

Next chance for a Chisel based Tiny Tapeout. Start with the official template from https://github.com

5/15/24

Martin Schoeberl

4/25/24

DSD Special Session on Chisel

Hi all, this is a gently reminder for a submission of a paper to the special session on Chisel at the

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DSD Special Session on Chisel

Hi all, this is a gently reminder for a submission of a paper to the special session on Chisel at the

4/25/24

Martin Schoeberl

4/22/24

DSD special session on Chisel

Dear all, this is a reminder to submit papers to the special session on Chisel at DSD 2024. See more

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DSD special session on Chisel

Dear all, this is a reminder to submit papers to the special session on Chisel at DSD 2024. See more

4/22/24

4/16/24

Is chisel supporting blackbox for .systemVerilog?

Dear Community, Is chisel support .sv files as blackbox? if yes what version of chisel?.

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Is chisel supporting blackbox for .systemVerilog?

Dear Community, Is chisel support .sv files as blackbox? if yes what version of chisel?.

4/16/24

Martin Schoeberl

4/8/24

Chisel projects on Tiny Tapeout 06

Hi all, it is time for Chisel to get Tiny. A Chisel template is available, just in time, for Tiny

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Chisel projects on Tiny Tapeout 06

Hi all, it is time for Chisel to get Tiny. A Chisel template is available, just in time, for Tiny

4/8/24

4/2/24

BoringUtils.bore() is depricated, example of how to translate into modern speak?

Silly question: is there an example somewhere of how to switch BoringUtils.bore() deprecated syntax

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BoringUtils.bore() is depricated, example of how to translate into modern speak?

Silly question: is there an example somewhere of how to switch BoringUtils.bore() deprecated syntax

4/2/24

3/27/24

Chisel 5 and blackbox an .SV

Can chisel (v5) handle blackbox as .sv files? because i only found examples with .v files

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Chisel 5 and blackbox an .SV

Can chisel (v5) handle blackbox as .sv files? because i only found examples with .v files

3/27/24

Øyvind Harboe, Øystein Hovind3

3/6/24

Scala 3 and Chisel

Thanks! On Wednesday, March 6, 2024 at 10:28:57 AM UTC+1 oys...@ascenium.com wrote: Jack Koenig

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Scala 3 and Chisel

Thanks! On Wednesday, March 6, 2024 at 10:28:57 AM UTC+1 oys...@ascenium.com wrote: Jack Koenig

3/6/24

Nick Gian, Martoni5

2/27/24

How to use floating point & fixed point

I have run the generating stuff but i want to run a chisel test in hardfloat. Can you help me how to

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How to use floating point & fixed point

I have run the generating stuff but i want to run a chisel test in hardfloat. Can you help me how to

2/27/24

2/27/24

Can ChiselTest generate testbench verilog file?

Hello chisel community, Can chiselTest generate testbench verilog file? lf yes how?

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Can ChiselTest generate testbench verilog file?

Hello chisel community, Can chiselTest generate testbench verilog file? lf yes how?

2/27/24

2/12/24

I want to compile and use FixedPoint & hardFloat for every project

I am using Chisel 3.6 and i want to use those 2 https://github.com/ucb-bar/fixedpoint/tree/chisel6?

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I want to compile and use FixedPoint & hardFloat for every project

I am using Chisel 3.6 and i want to use those 2 https://github.com/ucb-bar/fixedpoint/tree/chisel6?

2/12/24

qwer trump (zsjj), … Dmitry Belimov4

2/4/24

chiseltest failed on chisel 6.0

Hi All, Is it possible to transform Chisel code to C++ sources without iverilator? Why I ask this

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chiseltest failed on chisel 6.0

Hi All, Is it possible to transform Chisel code to C++ sources without iverilator? Why I ask this

2/4/24

1/23/24

verilog output with Chisel v5.1.0

I am using the chisel-template gcd module and see that I can generate a system verilog file. using:

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verilog output with Chisel v5.1.0

I am using the chisel-template gcd module and see that I can generate a system verilog file. using:

1/23/24

Martin Schoeberl

1/23/24

bit order on asUInt

Hi all, I am wondering why the mapping of a Vec to UInt is different from mapping a Bundle: val vec =

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bit order on asUInt

Hi all, I am wondering why the mapping of a Vec to UInt is different from mapping a Bundle: val vec =

1/23/24

1/22/24

Black-Box files cannot generate in one verilog files, when using chisel5

Hello, I am trying to bump from chisel 3.5.6 to chisel5. However, when I try to generate all code in

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Black-Box files cannot generate in one verilog files, when using chisel5

Hello, I am trying to bump from chisel 3.5.6 to chisel5. However, when I try to generate all code in

1/22/24

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