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May 26

Grouping Modules

Hello, I have a question regarding grouping of modules into a submodule. If I have the following:

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Grouping Modules

Hello, I have a question regarding grouping of modules into a submodule. If I have the following:

May 26

Warren Savage, … Øyvind Harboe4

May 18

Chiseltest performance for representation of memories

What I did when I needed gigabytes of memory for a design, is that I implement the memory in C++

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Chiseltest performance for representation of memories

What I did when I needed gigabytes of memory for a design, is that I implement the memory in C++

May 18

ashrir...@gmail.com, Øyvind Harboe2

May 7

Left shift possible code gen error

That looks correct to me. Maybe a little bit surprising, but correct. Can you elaborate on why this

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Left shift possible code gen error

That looks correct to me. Maybe a little bit surprising, but correct. Can you elaborate on why this

May 7

Øyvind Harboe4

Apr 28

FlatIO problem with Chisel 3.5.3

Another error I see: [info] firrtl.passes.CheckHighFormLike$UndeclaredReferenceException: @[FooUnit.

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FlatIO problem with Chisel 3.5.3

Another error I see: [info] firrtl.passes.CheckHighFormLike$UndeclaredReferenceException: @[FooUnit.

Apr 28

Apr 26

Chisel v3.5.3 has been released!

Hello Chiselers, I am very delighted to announce that we have released v3.5.3 of the various Chisel-

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Chisel v3.5.3 has been released!

Hello Chiselers, I am very delighted to announce that we have released v3.5.3 of the various Chisel-

Apr 26

ashrir...@gmail.com, Martoni3

Apr 22

illegal cyclic reference to Module

That was a typo in my question description. But the issue still persists. Here is more strangeness 1)

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illegal cyclic reference to Module

That was a typo in my question description. But the issue still persists. Here is more strangeness 1)

Apr 22

Mar 18

Is there a way to convert FIRRTL to Yosys json file without Yosys?

I would like to use https://github.com/nturley/netlistsvg to generate diagrams. Is there a way to

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Is there a way to convert FIRRTL to Yosys json file without Yosys?

I would like to use https://github.com/nturley/netlistsvg to generate diagrams. Is there a way to

Mar 18

talco...@gmail.com

Mar 4

Tensil open source ML inference accelerator

Hey everyone, We've released Tensil v1.0.0, an open source machine learning inference accelerator

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Tensil open source ML inference accelerator

Hey everyone, We've released Tensil v1.0.0, an open source machine learning inference accelerator

Mar 4

Mar 3

Absorb wire for IO blackbox connection

Hello, I have a problem with the last version of Gowin EDA synthesizer (1.9.8.03) as I explained on

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Absorb wire for IO blackbox connection

Hello, I have a problem with the last version of Gowin EDA synthesizer (1.9.8.03) as I explained on

Mar 3

Mar 1

binary literals

if i have x value. as follow: val x = UInt("b1010", 12) how can i take the first 2 bits

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binary literals

if i have x value. as follow: val x = UInt("b1010", 12) how can i take the first 2 bits

Mar 1

Feb 17

sv2chisel 0.5.0 release

Dear Chisel community, I am quite proud to announce the first proper release of sv2chisel, the

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sv2chisel 0.5.0 release

Dear Chisel community, I am quite proud to announce the first proper release of sv2chisel, the

Feb 17

Feb 10

Deduplication and unused outputs of modules

Deduplication doesn't take into account unused values. So if I have module where an output is

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Deduplication and unused outputs of modules

Deduplication doesn't take into account unused values. So if I have module where an output is

Feb 10

Øyvind Harboe2

Feb 10

These error were all real problems in the unit-test code. Neat feature! Otherwise everything worked

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These error were all real problems in the unit-test code. Neat feature! Otherwise everything worked

Feb 10

Feb 7

Chisel v3.5.1 has been released!

Hello everyone, I am very delighted to announce that we have released v3.5.1 of the various Chisel-

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Chisel v3.5.1 has been released!

Hello everyone, I am very delighted to announce that we have released v3.5.1 of the various Chisel-

Feb 7

Warren Savage, Kevin Laeufer2

Feb 6

Examples of using traits to modify published classes?

Hi Warren, My advice for parameterizing modules would be to use plain good-old case classes with

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Examples of using traits to modify published classes?

Hi Warren, My advice for parameterizing modules would be to use plain good-old case classes with

Feb 6

Øyvind Harboe, Jack Koenig4

Jan 29

0 bit wide integers

That's good to hear! Looking forward to this feature :-) The problem with not having zero width

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0 bit wide integers

That's good to hear! Looking forward to this feature :-) The problem with not having zero width

Jan 29

Øyvind Harboe, Jack Koenig2

Jan 28

Scala 2.12 and 2.13 problems with publishLocal?

Yes these instructions don't work as well anymore since we publish SNAPSHOTs in CI. We need to

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Scala 2.12 and 2.13 problems with publishLocal?

Yes these instructions don't work as well anymore since we publish SNAPSHOTs in CI. We need to

Jan 28

Øyvind Harboe, Jack Koenig3

Jan 27

The case of the missing stack trace

This is a fantastic question, I've opened a PR to chiseltest to add instructions for this

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The case of the missing stack trace

This is a fantastic question, I've opened a PR to chiseltest to add instructions for this

Jan 27

Øyvind Harboe, … Jack Koenig6

Jan 27

Another case of problems with Vec.toSeq

Thanks! I have closed the PR. Before the issues with the Scala compiler/type checking is fully

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Another case of problems with Vec.toSeq

Thanks! I have closed the PR. Before the issues with the Scala compiler/type checking is fully

Jan 27

Martin Schoeberl, Martoni3

Jan 26

3rd Edition of the Chisel Book is out

Hi Martoni, Amazon did not update the cover and not yet the looking inside. However, it is the third

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3rd Edition of the Chisel Book is out

Hi Martoni, Amazon did not update the cover and not yet the looking inside. However, it is the third

Jan 26

Øyvind Harboe, Jack Koenig2

Jan 25

Chisel v3.5.0 testing

Thank you for letting us know and glad to hear! On Tue, Jan 25, 2022 at 7:15 AM Øyvind Harboe <

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Chisel v3.5.0 testing

Thank you for letting us know and glad to hear! On Tue, Jan 25, 2022 at 7:15 AM Øyvind Harboe <

Jan 25

Martin Schoeberl, … Richard Lin3

Jan 19

If I remember correctly, when these were first introduced, the idea was to use .U for numeric

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If I remember correctly, when these were first introduced, the idea was to use .U for numeric

Jan 19

Jan 19

Chisel v3.5.0 has been released!

Hello everyone, I am very delighted to announce that we have released v3.5.0 of the various Chisel-

unread,

Chisel v3.5.0 has been released!

Hello everyone, I am very delighted to announce that we have released v3.5.0 of the various Chisel-

Jan 19

Øyvind Harboe2

Jan 12

Chisel 3.5.0-RC2 produces double underscores with BoringUtils, breaking Verilator

Hacked up a unit-test pull request that is failing: https://github.com/chipsalliance/chisel3/pull/

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Chisel 3.5.0-RC2 produces double underscores with BoringUtils, breaking Verilator

Hacked up a unit-test pull request that is failing: https://github.com/chipsalliance/chisel3/pull/

Jan 12

Øyvind Harboe, Schuyler Eldridge5

Jan 4

Any way to get rid of superfluous wires on module instantitation?

> On Jan 3, 2022, at 10:21, Øyvind Harboe <oyvindharboe@gmail.com> wrote: > > I took

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Any way to get rid of superfluous wires on module instantitation?

> On Jan 3, 2022, at 10:21, Øyvind Harboe <oyvindharboe@gmail.com> wrote: > > I took

Jan 4

Øyvind Harboe, … Michael Etzkorn6

12/30/21

FIR example on the Chisel 3 website with more idiomatic Scala functional programming concepts

I did find one of the original versions of the FIR example in the Berkeley Chisel Tutorial paper from

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FIR example on the Chisel 3 website with more idiomatic Scala functional programming concepts

I did find one of the original versions of the FIR example in the Berkeley Chisel Tutorial paper from

12/30/21

Øyvind Harboe2

12/25/21

Caching of tests in Chisel 3.5.0-RC2

Ah... BoringUtils.bore() yield non-idempotent names. For instance, depending on whether you invoke

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Caching of tests in Chisel 3.5.0-RC2

Ah... BoringUtils.bore() yield non-idempotent names. For instance, depending on whether you invoke

12/25/21

12/21/21

Chisel v3.5.0-RC2 has been released

Hello everyone, We have released a major version release candidate of the various Chisel-related

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Chisel v3.5.0-RC2 has been released

Hello everyone, We have released a major version release candidate of the various Chisel-related

12/21/21

12/16/21

Don't instantiate Module()s inside when() statements

So I did this and I got no compilation error, but of course it didn't work. This made me curious:

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Don't instantiate Module()s inside when() statements

So I did this and I got no compilation error, but of course it didn't work. This made me curious:

12/16/21

12/16/21

Confusing error message on unassigned inferred UInt() input

I've discovered that when I get error messages about uninferred widths, it can be because that

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Confusing error message on unassigned inferred UInt() input

I've discovered that when I get error messages about uninferred widths, it can be because that

12/16/21

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