chisel-users

1–30 of 957

0 selected

May 25

Gemmini test have waveform but not have data in it

Hello everyone, I wrote my own Gemini test in :“bareMetalC/matrix_add"(is attacked below), “”

unread,

Gemmini test have waveform but not have data in it

Hello everyone, I wrote my own Gemini test in :“bareMetalC/matrix_add"(is attacked below), “”

May 25

Oğuzhan Canpolat2

May 20

Declare and Connect Ports Parametrically (Chipyard Automatic ILA Core Generation)

Hi, I got around the problem by having a predeclared Sequence of probes and allowing debugging of

unread,

Declare and Connect Ports Parametrically (Chipyard Automatic ILA Core Generation)

Hi, I got around the problem by having a predeclared Sequence of probes and allowing debugging of

May 20

May 5

Chisel v3.6.0 has been released!

Howdy Chiselers, I am very delighted to announce that we have released v3.6.0 of the various Chisel-

unread,

Chisel v3.6.0 has been released!

Howdy Chiselers, I am very delighted to announce that we have released v3.6.0 of the various Chisel-

May 5

Apr 26

Error when run make=CONFIG=GCDAXI4BlackBoxRocketConfig debug

hello everyone, i want to adding my own Verilog in Chipyard, and implemented the correct stéps in

unread,

Error when run make=CONFIG=GCDAXI4BlackBoxRocketConfig debug

hello everyone, i want to adding my own Verilog in Chipyard, and implemented the correct stéps in

Apr 26

Øyvind Harboe, … Øyvind Harboe16

Apr 19

Negedge async reset?

Here you go: https://groups.google.com/g/chisel-users/c/IYZ8FWGcdkw On Friday, April 14, 2023 at 8:06

unread,

Negedge async reset?

Here you go: https://groups.google.com/g/chisel-users/c/IYZ8FWGcdkw On Friday, April 14, 2023 at 8:06

Apr 19

Apr 17

Method to compare Chisel vs. manually written Verilog

The example is a simple statemachine that detects 0xdeadbeef. In this post, I want to show a method

unread,

Method to compare Chisel vs. manually written Verilog

The example is a simple statemachine that detects 0xdeadbeef. In this post, I want to show a method

Apr 17

Martin Schoeberl

Apr 11

Deadline extension for: Digital Design and Verification with Chisel (DDVC)

Call for papers: Digital Design and Verification with Chisel (DDVC) https://dsd-seaa2023.com/ddvc/

unread,

Deadline extension for: Digital Design and Verification with Chisel (DDVC)

Call for papers: Digital Design and Verification with Chisel (DDVC) https://dsd-seaa2023.com/ddvc/

Apr 11

Jack Koenig, Øyvind Harboe2

Apr 11

Chisel v3.6.0-RC3 has been released!

I tried it: the SystemVerilog output from LLVM CIRCT is unchanged in my case. The only thing I had to

unread,

Chisel v3.6.0-RC3 has been released!

I tried it: the SystemVerilog output from LLVM CIRCT is unchanged in my case. The only thing I had to

Apr 11

Warren Savage, … Jack Koenig4

Apr 4

Running verilated chiseltest outside of sbt?

I apologize that it took this long for Warren's email to get through. This response was

unread,

Running verilated chiseltest outside of sbt?

I apologize that it took this long for Warren's email to get through. This response was

Apr 4

Øyvind Harboe, Schuyler Eldridge2

Apr 4

Can I use LLVM CIRCT without downloading firtool and putting it in the path?

This is not available now, but is possible. I think it's something like you include multiple Jars

unread,

Can I use LLVM CIRCT without downloading firtool and putting it in the path?

This is not available now, but is possible. I think it's something like you include multiple Jars

Apr 4

Martin Schoeberl

Mar 24

Call for papers: Digital Design and Verification with Chisel (DDVC)

Call for papers: Digital Design and Verification with Chisel (DDVC) https://dsd-seaa2023.com/ddvc/

unread,

Call for papers: Digital Design and Verification with Chisel (DDVC)

Call for papers: Digital Design and Verification with Chisel (DDVC) https://dsd-seaa2023.com/ddvc/

Mar 24

Øyvind Harboe, … Jack Koenig7

Mar 20

Chisel v3.6.0-RC2 example of slow verilator compilation

Awesome to hear :) Thanks Øyvind! On Mon, Mar 20, 2023 at 6:37 AM Øyvind Harboe <oyvindharboe@

unread,

Chisel v3.6.0-RC2 example of slow verilator compilation

Awesome to hear :) Thanks Øyvind! On Mon, Mar 20, 2023 at 6:37 AM Øyvind Harboe <oyvindharboe@

Mar 20

Mar 19

LLVM CIRCT generates an empty .v file as awell as a .sv file

When I generate .sv file with LLVM CIRCT, I get an empty .v file alongside the .sv file. Is this

unread,

LLVM CIRCT generates an empty .v file as awell as a .sv file

When I generate .sv file with LLVM CIRCT, I get an empty .v file alongside the .sv file. Is this

Mar 19

Jack Koenig, … Øyvind Harboe11

Mar 15

Chisel v3.6.0-RC2 has been released!

Yes: a g++ segfault is a g++ bug. However, verilator can generate C++ code that is atypical and

unread,

Chisel v3.6.0-RC2 has been released!

Yes: a g++ segfault is a g++ bug. However, verilator can generate C++ code that is atypical and

Mar 15

Øyvind Harboe, … Øyvind Harboe3

Mar 14

Chisel v3.6.0-RC2 - chiseltest doesn't use LLVM CIRCT

Thanks! tir. 14. mar. 2023, 17:11 skrev Kevin Laeufer <lae...@berkeley.edu>: Hi Øyvind,

unread,

Chisel v3.6.0-RC2 - chiseltest doesn't use LLVM CIRCT

Thanks! tir. 14. mar. 2023, 17:11 skrev Kevin Laeufer <lae...@berkeley.edu>: Hi Øyvind,

Mar 14

Feb 24

Chisel VS spinalHDL

Dear all, I'm new to chisel and i wanted to have your user feed-back about chisel and the

unread,

Chisel VS spinalHDL

Dear all, I'm new to chisel and i wanted to have your user feed-back about chisel and the

Feb 24

Jack Koenig, Øyvind Harboe4

Feb 21

Chisel v3.6.0-RC1 has been released!

Thank you as always for the bump (and bug!) reports Øyvind, they are extremely helpful. At a minimum,

unread,

Chisel v3.6.0-RC1 has been released!

Thank you as always for the bump (and bug!) reports Øyvind, they are extremely helpful. At a minimum,

Feb 21

Øyvind Harboe, … Øyvind Harboe5

Feb 21

Chisel 3.6.0-RC1 - alternative to forceName() for MixedVec()?

Thanks! Including link to github issue you filed: https://github.com/chipsalliance/chisel3/issues/

unread,

Chisel 3.6.0-RC1 - alternative to forceName() for MixedVec()?

Thanks! Including link to github issue you filed: https://github.com/chipsalliance/chisel3/issues/

Feb 21

Øyvind Harboe, … Øyvind Harboe6

Feb 17

v3.6.0-M2 and LLVM CIRCT 1.30.0 problem

👍 Nice! That DontCare requirement always looked bit odd. fre. 17. feb. 2023, 17:22 skrev Schuyler

unread,

v3.6.0-M2 and LLVM CIRCT 1.30.0 problem

👍 Nice! That DontCare requirement always looked bit odd. fre. 17. feb. 2023, 17:22 skrev Schuyler

Feb 17

Feb 16

LLVM CIRCT and OpenROAD/yosys

OpenROAD (and many projects besides) use yosys. yosys does not have full fledged System Verilog

unread,

LLVM CIRCT and OpenROAD/yosys

OpenROAD (and many projects besides) use yosys. yosys does not have full fledged System Verilog

Feb 16

Øyvind Harboe, … Schuyler Eldridge15

Feb 13

v3.6.0-M2 and BoringUtils and LLVM CIRCT

So I think the problem has to do with width inference, but not exclusively. Defining wires with

unread,

v3.6.0-M2 and BoringUtils and LLVM CIRCT

So I think the problem has to do with width inference, but not exclusively. Defining wires with

Feb 13

HyperDbg Debugger

Jan 25

Create verilog testbenches from Chisel tests

Hi, I have a question that you guys might know its answer. I already test my design by using

unread,

Create verilog testbenches from Chisel tests

Hi, I have a question that you guys might know its answer. I already test my design by using

Jan 25

Jack Koenig, Øyvind Harboe3

Jan 19

Chisel v3.5.6 has been released!

Answering my own question. This seems to work: "chisel3" -> "3.6.0-M2", "

unread,

Chisel v3.5.6 has been released!

Answering my own question. This seems to work: "chisel3" -> "3.6.0-M2", "

Jan 19

Øyvind Harboe2

12/23/22

Annotated with multiple force names

Hmmm..... this works fine in a small example, I can change both IO pins and module instance names.

unread,

Annotated with multiple force names

Hmmm..... this works fine in a small example, I can change both IO pins and module instance names.

12/23/22

12/7/22

Adding Static Delay in Arbiter and Debugging TIleLink

Hi, I'm trying to add static delay to the Arbiter object in TileLink: https://github.com/

unread,

Adding Static Delay in Arbiter and Debugging TIleLink

Hi, I'm trying to add static delay to the Arbiter object in TileLink: https://github.com/

12/7/22

Øyvind Harboe, Warren Savage2

12/2/22

Latches in Chisel?

Oh for God's sake, I hope Chisel never supports native latches. The lack of such Verilog-ish

unread,

Latches in Chisel?

Oh for God's sake, I hope Chisel never supports native latches. The lack of such Verilog-ish

12/2/22

Javed Osmany, Øyvind Harboe2

11/24/22

Mapping chisel assert(..) statement to assertion in generated Verilog/SVerilog code

Yes, that should be possible. Could you try to write up the example that is causing difficulties here

unread,

Mapping chisel assert(..) statement to assertion in generated Verilog/SVerilog code

Yes, that should be possible. Could you try to write up the example that is causing difficulties here

11/24/22

Øyvind Harboe, Schuyler Eldridge5

11/22/22

Chisel 3.6 roadmap, BoringUtils and LLVM CIRCT

I don't have enough relevant experience to articulate such a PR in a reasonable amount of time...

unread,

Chisel 3.6 roadmap, BoringUtils and LLVM CIRCT

I don't have enough relevant experience to articulate such a PR in a reasonable amount of time...

11/22/22

11/18/22

Generate emulator code from Chisel

Sorry, typo. That should have said that Chisel3 does NOT generate the C++ & emulator back-end

unread,

Generate emulator code from Chisel

Sorry, typo. That should have said that Chisel3 does NOT generate the C++ & emulator back-end

11/18/22

11/18/22

CHisel/Sbt generating C++ code where an undefined class is being used

Hello I am trying to pipe-flush the Chisel front-end flow. Taken the existing ALU block and generated

unread,

CHisel/Sbt generating C++ code where an undefined class is being used

Hello I am trying to pipe-flush the Chisel front-end flow. Taken the existing ALU block and generated

11/18/22

Search

Clear search

Close search

Google apps

Main menu