Connecting axi4_mem_0_clock to Vivado AXI4 controller

[TOBIAS KIM]

I'm utilizing Vivado and a ZCU102 board to implement a rocket chip. However, when connecting the rocket's external memory AXI port with Xilinx's DDR4 memory controller AXI port, I'm confused as to where I should connect the Rocket's axi4_mem_0_clock. Should I connect axi4_mem_0_clock  to the RAM controller's c0_sys_clk_i input or should I just leave axi4_mem_0_clock unconnected?

[Tayyeb Mahmood]

connecting axi to Xilinx ips should utilize AXI SmartConnect IP available in Block Design.

[TOBIAS KIM]

Connecting with the smart connect makes things a lot easier. Thank you!

[连浩丞]

Are you generating the bitstream through the FPGA script in chipyard? I'm also in the process of burning the rocket chip onto the zcu102, but I noticed that it requires writing a lot of peripheral chisel code based on the characteristics of the zcu102. If you're doing it this way, could you share your code with me?