Synthesis with Sky-130+OpenRoad for TinyRocket and GemminiSoCConfig

[chihyu]

Hi, all

I'm trying to synthesis the TinyRocket SoC using sky-130+openroad. In the ChipTop.synth_stat.txt file, I noticed that many modules are missing area reports, such as AsyncResetSynchronizerShiftReg_w1_d3_i0, GenericDigitalInIOCell, and EICG_wrapper. Some of them are composed of FFs like $DFF_PP0 or other types of FFs, which don't have definitions in the syn_rundir/. Is this expected behavior? Will it cause any issues during the P&R stage? Even though the area for these submodules is missing, the synth_stat.txt still shows the area for the parent module, which confuses me.

If I use spike or verilator to verify the functionality and cycle-accurate performance of the mapped.v file, would that work in theory?

I noticed that in chipyard/.conda-env/lib/python3.10/site-packages/hammer/technology/sky130/defaults.yml, there's a line that says "dffram_lib: "/path/to/dffram/compiler/build" # DFFRAM currently not supported". Is this the reason why yosys couldn't map the DFFs?

My second question is about synthesizing the CustomGemminiSoCConfig SoC using sky-130+openroad. When I run "make buildfile tutorial=sky130-openroad", I get errors like the following:

"generators/gemmini/src/main/scala/gemmini/DMA.scala:560:32: error: unsupported packed array expression generators/gemmini/src/main/scala/gemmini/DMA.scala:560:32: note: see current operation: %1311 = "comb.mux"(%1000, %1309, %1310) <{twoState}> : (i1, !hw.array<4xi5>, !hw.array<4xi5>) -> !hw.array<4xi5>"

Is it currently possible to synthesize the Gemmini design using openroad+sky130?

Any help and suggestions would be greatly appreciated.

Thanks, 

Andy