Ice-NIC Base addr/ MMIO register mapping

[Varun Gandhi]

Hi,

I wanted to clarify a basic detail about IceNet NIC — In NIC.scala I see the following lines of chisel code:

trait CanHavePeripheryIceNIC { this: BaseSubsystem =>

private val address = BigInt(0x10016000)

private val portName = "Ice-NIC”

Is 0x10016000 the base address of the NIC device and the absolute virtual address of MMIO registers can be computed with this base val

e.g., 0x00 —> Seq(RegFrield.w(NET_IF_WIDTH, sendReqQueue.io.enq)) — Does this line of code imply that writing to 0x10016000 would enqueue the 64-bit value to the send request queue?

Best,

Varun