Hey Jerry,
Thanks for the response. I spent a bit of time going over the chipyard repo since your response (thanks again). I compiled a variety of the examples provided (Ibex, write zero, etc) but they are currently doing a bit more than what I'm after at the moment. My goal at this point in time is to do something incredibly simple- connect some sort of module to some sort of memory via TileLink and perform arbitrary reads and writes. A 1 to 1 connection at this time is totally fine. Is there a way of doing this without instantiating my simple module as a chipyard tile as per "
https://chipyard.readthedocs.io/en/stable/Customization/Custom-Core.html"? In other words, is there a way to build a simple TL module in the same way the chisel bootcamp does but in newer versions of chisel?
As far as I'm aware, building simulations in sims/verilator as make CONFIG=<config name> requires the module to be placed as a config in chipyard repo, which intern requires the module to be instantiated as a tile. I'm inclined to believe there is a simpler way. Please let me know. Take care