TL interconnect under chisel 6.0

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hakam atassi

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Jul 23, 2024, 7:26:24 AM (4 days ago) Jul 23
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Hello,

I've found that the vast majority of the chipyard repo is under chisel 3, including the GCD MMIO generator example. However, I see that newer versions of the chipyard repo (ie, versions past 1.11.0) seem to possibly support newer versions of chisel.

I have custom standalone project that is under chisel 6.0. How would I go about using freechips tilelink in my project? Is that currently a possibility? Thanks in advance. Take care.



Jerry Zhao

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Jul 23, 2024, 2:11:20 PM (4 days ago) Jul 23
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Yes, just integrate your project into a modern Chipyard (latest main). RTL simulations compile with Chisel 6.0.

-Jerry

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hakam atassi

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Jul 25, 2024, 5:52:31 PM (2 days ago) Jul 25
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Hey Jerry,

Thanks for the response. I spent a bit of time going over the chipyard repo since your response (thanks again). I compiled a variety of the examples provided (Ibex, write zero, etc) but they are currently doing a bit more than what I'm after at the moment. My goal at this point in time is to do something incredibly simple- connect some sort of module to some sort of memory via TileLink and perform arbitrary reads and writes. A 1 to 1 connection at this time is totally fine. Is there a way of doing this without instantiating my simple module as a chipyard tile as per "https://chipyard.readthedocs.io/en/stable/Customization/Custom-Core.html"? In other words, is there a way to build a simple TL module in the same way the chisel bootcamp does but in newer versions of chisel? 

As far as I'm aware, building simulations in sims/verilator as make CONFIG=<config name> requires the module to be placed as a config in chipyard repo, which intern requires the module to be instantiated as a tile. I'm inclined to believe there is a simpler way. Please let me know. Take care
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