Dummy TestIO in the ChipTop module

[Brendon Chetwynd]

I need to create some Test I/O @ the ChipTop module that does not get routed any further in the design, but does not get optimized by the FIRRTL compiler.

I am guessing I should be able to create an IOBinder to accomplish this, but I haven't quite found an example of the appropriate constructs.

[Jerry Zhao]

On Tue, Jan 11, 2022 at 10:37 AM Brendon Chetwynd <bche...@gmail.com> wrote:

I need to create some Test I/O @ the ChipTop module that does not get routed any further in the design, but does not get optimized by the FIRRTL compiler.

I am guessing I should be able to create an IOBinder to accomplish this, but I haven't quite found an example of the appropriate constructs.

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[Brendon Chetwynd]

Looks like an empty response?

[Jerry Zhao]

In chipyard/generators/chipyard/src/main/scala/example/GCD.scala, look at the CanHavePeripheryGCDModuleImp trait

You want to write your own trait following this pattern.

trait HasMyTestIO extends LazyModuleImp {
  val test_io = IO(new TestIO)
  dontTouch(test_io)
}

Then in DigitalTop.scala, add the trait to DigitalTopModule.

On Tue, Jan 11, 2022 at 10:37 AM Brendon Chetwynd <bche...@gmail.com> wrote:

I need to create some Test I/O @ the ChipTop module that does not get routed any further in the design, but does not get optimized by the FIRRTL compiler.

I am guessing I should be able to create an IOBinder to accomplish this, but I haven't quite found an example of the appropriate constructs.

[Brendon Chetwynd]

Thanks, Jerry.

Still navigating the various Traits, classes, etc.

Example code:

import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._

trait TestIO extends Bundle {
  val testio_0 = Input(Bool())
  val testio_1 = Input(Bool())
  val testio_2 = Input(Bool())
  val testio_3 = Input(Bool())
}

trait HasTestIO extends LazyModuleImp {

val test_io = IO(new TestIO)
dontTouch(test_io)
}

Build result:

[error] /home/user1/chipyard/generators/asicblocks/src/main/scala/testIO.scala:25:19: trait TestIO is abstract; cannot be instantiated
[error]         val test_io = IO(new TestIO)
[error]                          ^
[error] one error found

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[Jerry Zhao]

TestIO should not be a trait.

class TestIO extends Bundle {...

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[Brendon Chetwynd]

Jerry.... that solved the problem, now onto IOBinders.

I need to create GenericDigitalGPIOCells for each one, understanding that a lot of IOCell pins will be unused/fixed.

I started by looking at the WithGPIOCells and WithSPIFlashIOCells examples in IOBinders...

Given the following testIO.scala:

import chisel3._
import chisel3.util._
import chisel3.experimental.{Analog, IO}
import freechips.rocketchip.diplomacy._

class TestIO extends Bundle {
  val testio = Vec(4, Analog(1.W)) // Not using Analog(4.W) because we can't connect these to IO cells
}

trait HasTestIO extends LazyModuleImp {
  val testio = IO(new TestIO)
  dontTouch(testio)
}

I was tryin to use the following to instantiate an I/O cep for 

class WithTestIOCells extends OverrideIOBinder({
  (system: HasTestIO) => {
    val (ports2d, cells2d) = system.testio.zipWithIndex.map({ case (testio, i) =>
      testio.zipWithIndex.map({ case (pin, j) =>
        val g = IO(Analog(1.W)).suggestName(s"testio_${i}_${j}")
        val iocell = system.p(IOCellKey).gpio().suggestName(s"iocell_testio_${i}_${j}")
        iocell.io.o := pin.o.oval
        iocell.io.oe := pin.o.oe
        iocell.io.ie := pin.o.ie
        pin.i.ival := iocell.io.i
        iocell.io.pad <> g
        (g, iocell)
      }).unzip
    }).unzip
    val ports: Seq[Analog] = ports2d.flatten
    (ports, cells2d.flatten)
  }
}) // WithTestIOCells

This fails with a whole lot of errors.... the first of which is :

 value zipWithIndex is not a member of myBlocks.testIO.TestIO
[error]     val (ports2d, cells2d) = system.testio.zipWithIndex.map({ case (testio, i) =>

There are some simpler Chisel constructions that I am missing, I am sure.

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[Michael Etzkorn]

So the problem with a fair number of the IOBinder examples is they're using parameterization you'll need to understand and implement into your IO to model your IOBinder after them.

The class IOCells either creates or inherits a function called makeIOs that returns a type with access to zipWithIndex (I still haven't learned much of the scala-land stuff, and haven't had need for level of IO parameterization things like GPIOCells and SPICells use, so I'm not gonna pretend I know how IOCells works). 

The good news is for punching out IO like this that aren't parameterized, you don't need to do anything with the config API (that p(IOCellKey) thing). You also don't use mapping or zip with index. In fact, since your testIO isn't an Option based IO and always included in the system, you should be able to do something as simple as:

class TestIO extends Bundle {

// added _ between test and io to make name look nicer in verilog

  val test_io = Vec(4, Analog(1.W)) // Not using Analog(4.W) because we can't connect these to IO cells

}

trait HasTestIO extends LazyModuleImp {

  val test_io = IO(new TestIO)

}

class TestIOPassthrough extends OverrideIOBinder({

    (system: HasTestIO) => {

        // clones the internal DigitalTopIO to make pins visible to ChipTop

        val test_io_temp = IO(DataMirror.internal.chiselTypeClone[TestIO](system.testio)).suggestName("my_block") // prefix to "test_io"

        test_io_temp <> system.testio // connecting ChipTop to DigitalTop

        (Seq(test_io_temp), Nil)      // return for harness binder

    }

})

The need for dontTouch isn't necessary once the pins are visible to ChipTop. Chipyard's main function will automatically mark ChipTop pins as DontTouch for you.

[Michael Etzkorn]

As a note, you'll need to add chisel3.experimental.DataMirror and chipyard.iobinders.OverrideIOBinder to your imports. 

[Brendon Chetwynd]

Michael,

 

That worked as advertised, but is not quite where I need to be.

 

Effectively, I would like to instantiate the following for all the dummy I/O.

 

GenericDigitalGPIOCell iocell_testio_0 (

    .pad(testio_0),

    .i(1’b0),

    .ie(1’b0),

    .o(),

    .oe(1’b1)

  );

 

Per the code you provided, I have a wire @ ChipTop directly passed to DigitalTop, where it goes nowhere.  

Actually, I want all my chip's I/O to use the GenericDigitalGPIOCell buffers, understanding the unidirectional ports, some of the cell's control signals will be fixed.

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[michael etzkorn]

I see. Simplest approach is to declare the GenericDigitalGPIOCell module in your LazyModuleImp and connect your testio to it.

Something like Example within your LazyModuleImp. (GenericDigitalGPIOCell already exists within IOCell.scala. I only added it as a blackbox for the scastie)

Assuming you want to parameterize the # of these, you'll want to use a for loop or something to declare each module and connect one of the io. 

[Brendon Chetwynd]

As it turns out, I successfully solved this problem using the following construct:

class WithTestIOStubs extends OverrideIOBinder({
  (system: DontTouch) => {
    val ports = IO(new Bundle {
      val io      = Vec(16, Analog(1.W))
      val mode    = Vec(4, Analog(1.W))
    }).suggestName(s"test")

    val iocells = ports.io.zipWithIndex.map { case (pin, i) =>
      val iocell = Module(new GenericDigitalGPIOCell).suggestName(s"iocell_testio_${i}")
      iocell.io.o  := false.B
      iocell.io.oe := true.B
      iocell.io.ie := false.B
      iocell.io.pad <> pin
      iocell
    }
    (Nil, iocells)
  }
})

Things have changed with Chipyard 1.10.0 that results in the IO cells being properly instantiated in ChipTop.sv, but it does not connect the pad to top level I/O.

Here is a snippet of my AbstractConfig:

...

  new chipyard.iobinders.WithDontTouchIOBinders ++
  new chipyard.iobinders.WithTestIOStubs ++

...

Any thoughts would be appreciated.

[Jerry Zhao]

Note that if you aren't planning on taping out your design, there's no need to use the GenericIOCells, you can just punch through IOs directly. There are a few "PunchThroughIOBinders" that do this.

-Jerry

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[Brendon Chetwynd]

Thanks,  Jerry.   This is a tapeout certain of the design 

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[Brendon Chetwynd]

Let's try this again.  Jerry, this is for a tapeout version of the design... so I need to instantiate stubbed version of GenericIOCells.

- Brendon

[Jerry Zhao]

Oh sorry, I didn't catch that something was still broken for you.

Can you try this:

```

class WithTestIOStubs extends OverrideIOBinder({
  (system: DontTouch) => {
    val ports = IO(new Bundle {
      val io      = Vec(16, Analog(1.W))
      val mode    = Vec(4, Analog(1.W))
    }).suggestName(s"test")

    val iocells = ports.io.zipWithIndex.map { case (pin, i) =>
      val iocell = Module(new GenericDigitalGPIOCell).suggestName(s"iocell_testio_${i}")
      iocell.io.o  := false.B
      iocell.io.oe := true.B
      iocell.io.ie := false.B
      iocell.io.pad <> pin
      iocell
    }

    (Seq(ports), iocells)
  }
})
```

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