Further question about Transmitting an executable binary to FPGA via Serial port

[Yue Cao]

Hello,

Currently, we're trying to transmit our binary to our design on FPGA VCU118, as we're encountering a problem with loading the program from an SD card and simulating the fesvr, we're wondering if we can directly send our binary via a UART port. I have your previous communication at

https://groups.google.com/g/chipyard/c/7w4xkMz_E14/m/bQaakOAWAAAJ

and checked the config TetheredChipLikeRocketConfig. 

However, I found that in the generated verilog file, the program binary is still transmitted via the fesvr module SimTSI, with some additional TSI-to-UART verilog modules. I want to know what will be the correct program that we should run on our host to transmit the binary via UART?

Thanks

Yue

[Yue Cao]

Does this process related to the uart_tsi here?

https://github.com/ucb-bar/testchipip/tree/master/uart_tsi

If yes, how should we implement this?

Thanks,

Yue

[Joonho Whangbo]

You should take a look at WithUartSerialTl

Joonho

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[Yue Cao]

No, I'm not talking about the internal conversion between UART and serialTL, for this part the current scala codes already solve my problem. Here I mean for the function of fesvr, though I cannot fully clarify its function, based on my observation in the waveform, it's adding tilelink-related information to the original program(address, mask, opcode, etc), which means it cannot be replaced by any arbitrary UART transmitter. In this case, I want to know if there's any document or information on how to implement this UART-based fesvr on our host.

Thanks,

Yue

[Yue Cao]

Thanks for your recommendation, the config that you mentioned gives the hardware implementation for the interface chip in FPGA to convert the UART inputs to serialTL version, but what I meant is this part in the scala code of ChipBringupHostConfig:

Based on this config, though the binary loading port of this bringup chip is UART, the driver of the UART ports are still SimTSI+UART-to-TSI hardware modules, which cannot be directly implemented on a host CPU with UART ports, where the strcuture can also be confirmed via the generated verilog code:

The part that I'm unclear about now is this part, namely the software driver in the host CPU to transmit binary to the UART interface. What I have found now is this description in testchipip github:

It seems that this is the software driver that I need and I have tried that the executable 'uart_tsi' can be generated in the latest chipyard environment. However, I haven't found any document or guidance on how to implement this on a host CPU and how should we place the executable binary for DUT so that this driver can load it. Could you please provide some suggestions on this?

Thanks,

Yue

On Wednesday, December 11, 2024 at 1:06:07 PM UTC+8 Joonho Whangbo wrote:

[Yue Cao]

Somehow I cannot reply to this conversation and all of my new messages got deleted. So I changed to a new account and also filed an issue on github.

Question about Transmitting an executable binary to FPGA via Serial port · Issue #2151 · ucb-bar/chipyard · GitHub

Let me reclarify my question again here:

In general, I want to implement my DUT in FPGA and transmit the executable binary for DUT using a host CPU via UART ports. Based on the suggestion in https://groups.google.com/g/chipyard/c/7w4xkMz_E14/m/bQaakOAWAAAJ, I have tried the chipyard config TetheredChipLikeRocketConfig and as mentioned by Joonho in my mailing list, the attribute WithUartSerialTl provides the FPGA-synthesizable hardware modules for converting UART to serialTL, so the FPGA implementation with UART port for binary receiving is complete.

However, the problem on the host side implementation still exists. The current driver implementation in the TetheredChipLikeRocketConfig is SimTSI + several hardware modules for TSI-to-UART conversion, where these hardware modules cannot be implemented on a host CPU.
Config setting:

Generated verilog code:

Therefore, I wonder if here exists a software driver for this condition. Based on my search, the 'uart_tsi' from testchipip github seems to match my need:
https://github.com/ucb-bar/testchipip/tree/master

I have successfully generated the executable for 'uart_tsi', but I haven't found any documents or guidance on how to apply this executable on the host CPU and how can it interact with our binary for DUT. Is there any suggestions on this condition?

Thanks,

Yue

[Yue Cao]

Somehow all of my previous messages got deleted. Can this one be seen?

On Wednesday, December 11, 2024 at 1:06:07 PM UTC+8 joonho.whangbo wrote: