Post Synthesis Simulation

[Christian Lanius]

Hi All,

I am attempting to push the MegaBoomConfig through our VLSI flow (not hammer). I am currently attempting to run post synthesis simulation for the design. The steps I did are:

Generate the chipyard.TestHarness.MegaBoomConfig.top.v

Add the EICG_wrapper, IOCell, plusarg_reader and ClockDividerN files

Replace the contents of the clock gating cell with the standard cell definition

Replace the contents of the IO cells with normal assignments

Replace the contents of the clock divider by a simple assign statement (I have checked the generated code, it only gets instantiated with a DIV of 1)

Mark the memory macros as black box

Synthesize the design with ChipTop as the top level (so I do not have to connect the multiple clocks etc by hand, the IO cells will be synthesized away)

Write a new target in the Makefile in sims/vcs, which looks the same as debug target, but adds the technology verilog and replaces the chipyard.TestHarness.MegaBoomConfig.top.v with the result of synthesis

Compile the simulator

Run the simulator with a RISCV program

Unfortunately, my simulation hangs and never finishes. As the way I added post synthesis simulation is hacky, I was hoping if you could give me some pointers how to perform post synthesis simulation. I would rather prefer not to use hammer, as our flow is silicon proven and the necessary validation to integrate/use hammer is quite significant.

Kind regards

Christian