Connecting BOOM tile with SRAM/DRAM - RocketChip

[Kelly Xu]

What is the best way to connect a BOOM tile directly with SRAM/DRAM and remove all other components? The goal is to generate the simplest possible SoC with just a core and memory. The current option is to write a custom top-level TestHarness file, Makefile, and subsystem containing the BOOM tile, existing SystemBus, and SRAM. We would need to set up the config fragments to not use AbstractConfig, as it’s based on BaseSubsystemConfig which has a lot of configurations dependent on the control bus, front bus, etc.

 
Another option would be to extract the necessary modules from the generated Verilog, from the default simulation design without the L2 cache.

 
If anyone has any advice on the best way to do this, it would be greatly appreciated!
Thank you so much!

[Kelly Xu]

[Jerry Zhao]

You can use config fragments to remove the L2, unnecessary devices, etc. This would be the best way.

-Jerry

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[Kelly Xu]

Thank you for the advice! We managed to generate a simple design with the config fragments, and isolated the remainder of what we needed through the Verilog modules.

Currently our problem is with adding a custom memory module to the isolated Boom Tile. We're trying to implement the TileLink communications on Channels A and D to communicate to the BoomTile directly. Is there a simpler way to add the TileLink protocol or remove it entirely?

Thanks! 

[Jerry Zhao]

I'm not sure what you are asking. Are you trying to implement a custom device in the memory system?

-Jerry

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[Kelly Xu]

Basically, yes. Instead of the memory modules provided, we want to connect our BoomTile to a custom DRAM, and we're having trouble with implementing the TileLink communications for the custom DRAM.