Signal in ClockSinkDomain_1 cannot be written from module ClockSinkDomain_1

[chihyu]

Hi,

I'm trying to put together a MMIO module with two DMA modules, one for reading and another for writing. I'm using Chisel and facing an issue with signal connections.

Here is a part of my code, 

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class BOXTL(params: BOXParams, beatBytes: Int)(implicit p: Parameters) extends ClockSinkDomain(ClockSinkParameters())(p) {
  val device = new SimpleDevice("BOX", Seq("me,BOX"))
  val node = TLRegisterNode(Seq(AddressSet(params.mmioAddr, params.mmioSize)), device, "reg/control", beatBytes=beatBytes)
  val read_dma_node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters(name = "ReadDMA", sourceId = IdRange(0, 1))))))
  val write_dma_node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters(name = "WriteDMA", sourceId = IdRange(0, 1))))))

  override lazy val module = new BOXImp
  class BOXImp extends Impl with HasBOXTopIO {
    val io = IO(new BOXTopIO(params.width))
    withClockAndReset(clock, reset) {
      val base = Reg(UInt(params.width.W))
      val instr = Wire(new DecoupledIO(UInt(params.width.W)))
      val result = Wire(new DecoupledIO(UInt(params.width.W)))
      val status = Wire(UInt(2.W))

      val box = LazyModule(new BOXMMIOChiselModule(params.width))
      val read_dma = LazyModule(new ReadDMA(read_dma_node, params.width))
      val write_dma = LazyModule(new WriteDMA(write_dma_node, params.width))

      val box_io = box.io
      val read_dma_io = read_dma.io
      val write_dma_io = write_dma.io

      // Read DMA Interconnection
      box_io.rd_input_ready := read_dma_io.input_ready
      read_dma_io.input_valid := box_io.rd_input_valid
      read_dma_io.base := box_io.rd_base
      box_io.rd_data_valid := read_dma_io.data_valid
      box_io.rd_data := read_dma_io.data
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I encountered an error when connecting box_io.rd_input_ready and read_dma_io.input_ready signals. The error message is:

caused by: chisel3.package$ChiselException: Connection between sink (ClockSinkDomain_1.boxIO.rd_input_ready: IO[Bool]) and source (ClockSinkDomain_1.readIO.input_ready: IO[Bool]) failed @: boxIO.rd_input_ready in ClockSinkDomain_1 cannot be written from module ClockSinkDomain_1.

box_io.rd_input_ready is an input signal for the box module, and read_dma_io.input_ready is an output signal for the read_dma module.
  
I'm a beginner in Chisel, any suggestion would be very helpful. Thank you!