Hello,
I am taping out a Chipyard design
and have technology-specific I/O pads in my design. Their max frequency
is much less than that of the rest of the design, and I want to put the
I/O pads in a separate clock domain. After reading through previous
posts, it seems like the TL serial link/JTAG have their own clocks and
are asynchronous from the rest of the system.
Is
this a correct interpretation? Does Chipyard already handle the clock
domain crossings between the interface pads and the rest of the system?
If not, is there an example of how to add this?
Thanks,
Kathleen