I/O Pad Clock Domain

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Kathleen Feng

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May 29, 2024, 9:33:38 PMMay 29
to Chipyard
Hello,

I am taping out a Chipyard design and have technology-specific I/O pads in my design. Their max frequency is much less than that of the rest of the design, and I want to put the I/O pads in a separate clock domain. After reading through previous posts, it seems like the TL serial link/JTAG have their own clocks and are asynchronous from the rest of the system.

Is this a correct interpretation? Does Chipyard already handle the clock domain crossings between the interface pads and the rest of the system? If not, is there an example of how to add this?

Thanks,

Kathleen

Jerry Zhao

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May 30, 2024, 1:15:49 PMMay 30
to chip...@googlegroups.com
> Is this a correct interpretation? Does Chipyard already handle the clock domain crossings between the interface pads and the rest of the system? If not, is there an example of how to add this?

Yeah this is right. JTAG provides its own clock externally via jtag.TCK, so you just have to limit that to what your pads can handle.
The only concerning signal is serial-TL, as you've mentioned. The default ChipLikeRocketConfig in upstream chipyard synchronizes the sertl lanes to the externally driven sertl clock, with an internal crossing to the rest of the digital side.

If you are doing a tapeout with Chipyard, you should look at the configs in ChipConfigs.scala. The ChipLikeRocketConfig is the closest "tapeout-ready" configuration. The ChipBringupHostConfig is a config of the FPGA-side bringup system. The TetheredChipLikeRocketConfig simulates the chip alongside the FPGA bringup harness, enabling early-stage RTL simulation of the entire bringup procedure.

-Jerry

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Kathleen Feng

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May 31, 2024, 4:34:02 PMMay 31
to 'Jerry Zhao' via Chipyard
Hi Jerry,

Great, thank you for the response and the pointers to existing configs!

Kathleen
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