Overriding verilog module name, not the instantiation

[Brendon Chetwynd]

.suggestName is a powerful tool for overriding default signal names and module instantiations. 

Is there a way of overriding the default module name and the generated verilog file?

For example, all of my peripherals use .generateSynchronousDomain.  As a result, the generated verilog files are named as follows:

ClockSinkDomain.sv

ClockSinkDomain_1.sv

ClockSinkDomain_2.sv

ClockSinkDomain_3.sv

...

Ideally, the module name and filename would be something like myFuncDomain and myFundDomain.sv

[Brendon Chetwynd]

.suggestName allows you to override a module instance name (from outside module)

desiredName allows you to override a module name from inside the module.

Unfortunately, I don't control the ClockDomain module... so is there anyway to execute something like desiredName from outside the module definition?

[Jerry Zhao]

There should be a parameter added to the Chisel constructor of ClockDomain to enable passing in a custom desiredName for the generated ClockDomain.
This should be added to rocket-chip.

-Jerry

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[Brendon Chetwynd]

Thanks, Jerry.  I am guessing there is no way of forcing an override from outside the module?

[Jerry Zhao]

I'm not aware of one. An API for naming ClockSinkDomains has been added to rocket-chip.

-Jerry

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