Question about IISWC 2021 tutorial

[Chao Gao]

Hi,

Sorry to bother you, I attend the IISWC tutorial, but I still have a few questions in mind,

1. About function simulation in spike:

a. building-spike: I saw in the script, we are using verilator to build the .h file and further build the spile, I wondered how this step works, and also what is usage of "software/gemmini-rocc-tests/include/gemmini_params.h" and "/software/gemmini-rocc-tests/include/gemmini.h" and all the other .h file in software/gemmini-rocc-tests/include purpose?

b. software test file: I guess that we should use gemmini_params.h to build spike simulator, I wondered that since the gemmini should work along the Rocket-chip, in that case, how can spike as an ISA simulator works in that scenario? (Sorry that I am still learning spike)

c. Using spike: I guess that using spike can be an easy way for me to work on ROCC design, I was wondering what should be the input to the spike simulator, is the ROCC ISA?

d. another simulator: I knew that spike is good for risc-v and ROCC testing, however, if I want to test multi-core or multi-accelerator performance, I heard that spike isn't friendly to cache coherency, I wondered is there any simulator that covers ROCC?

2. About training and inference Systolic array setting difference:

a. I saw that in snap-shot and build.sh file that training and inference are setting twice, I wondered is that because is there any special optimization in back-propagation part?

b. I remember that in the tutorial session, we talked about synchronization in Gemmini, I wondered that since Gemmini and Rocket-chip are both connected to L2 cache, how Gemmini and Rocket-chip achieve cache coherency?

3. About supporting DRAM simulator

a. I saw that in Midas we can simulate DDR3, I was wondering can we do simulation in DDR4/HBM in spike by connecting to DRAMsim2/Ramulator or we can print out the memory trace in spike?

Thanks for your patience

Best

[Hasan Genc]

1a. build-spike.sh: Our Chisel code generates a file called "gemmini_params.h" which is used to tell our software libraries exactly which features the Gemmini hardware supports, and how large it's scratchpad and spatial array are. Using the information in "gemmini_params.h", Gemmini's software library (which is nearly all contained within "gemmini.h"), decides how to block and tile the for-loops for our implementation of different DNN kernels like convolutions and matmuls.

1b. software test file: Spike was originally used to simulate RISC-V CPU instructions. However, it has since been extended to also simulate Hwacha and Gemmini instructions. So Spike is able to simulate both RISC-V CPU instructions (like in RocketChip), and also Gemmini instructions.

1c. using spike: The only input to Spike is a RISC-V binary. You can extend Spike with support for different accelerators (like we did for Gemmini), and whenever Spike encounters an instruction that it does not understand, it'll pipe it to your extension, which can interpret the bits in the instruction.

2a. I'm not sure what you mean by the "snap-shot", but we did add special optimizations for back-propagation. For example, we added support for transpose convolutions which are not usually used in inference, but are used in training.

2b. Gemmini and RocketChip achieve cache-coherency through the Tilelink protocol. Basically, Gemmini doesn't have to worry about coherency, because Tilelink handles it all for us :).

3a. That would be a great feature, but we don't have support for interfacing with DRAMsim2/Ramulator at this time.

Regards,

Hasan

[Jerry Zhao]

The default DRAM model in Chipyard RTL simulations is DRAMSim2. There is a DRAMSim2 ini file that can be edited to adjust memory characteristics.

-Jerry

--
You received this message because you are subscribed to the Google Groups "Chipyard" group.
To unsubscribe from this group and stop receiving emails from it, send an email to chipyard+u...@googlegroups.com.
To view this discussion on the web visit https://groups.google.com/d/msgid/chipyard/3886f06f-1327-4c60-8fa9-98b61b6ed429n%40googlegroups.com.

[Chao Gao]

Thanks guys,

Really appreciate your support,

I am more clear about the problem that I am trying to solve now.

Best

Chao

Jerry Zhao <J...@berkeley.edu>于2022年1月20日 周四下午11:32写道：

To view this discussion on the web visit https://groups.google.com/d/msgid/chipyard/CAC%2BpDSH-ui%3Don05FcJnuD7UU1h6d9je4MikwyVSLdbkT68t%2BGw%40mail.gmail.com.