How to run chipyard's unittest simulation in verilator?

[Jerry Ho]

I noticed that there are some unittest facility in chipyard, and in the variable.mk, if you set the default SUB_PROJECT as testchip, chipyard will instantiate the Testharness in chipyard.uniitest package:

class TestHarness(implicit val p: Parameters) extends Module {
  val io = IO(new Bundle { val success = Output(Bool()) })
  io.success := Module(new UnitTestSuite).io.finished
}

However, When I try to run make default in the sims/verilator folder, and it does indeed generated a executable: simulator-chipyard.unittest-TestChipUnitTestConfig, but If I just run it without providing any extra parameters, it will return very quickly, displaying the following:

This emulator compiled with JTAG Remote Bitbang client. To enable, use +jtag_rbb_enable=1.
Listening on port 33373

I actually add lots of chisel printfs in the TestHarness, and none of them are showing here. So, I wonder if any extra parameters needs to be passed to the verilator generated executable(simulator-chipyard.unittest-TestChipUnitTestConfig), so that the UnitTest can actually run?

Any help are very appreciated. Thanks!

[Jerry Zhao]

That should work... you can also try `run-binary BINARY=none`, which should definitely work.

-JErry

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