Push ASAP7 SRAM Macros into the P&R Flow

[Chen BAI]

Hi all,

I have used ASAP7 SRAM macros (https://github.com/ucb-bar/hammer/tree/master/src/hammer-vlsi/technology/asap7) to synthesize a BOOM SoC. (I can use the synthesized BOOM SoC to simulate with different benchmarks)

I use Genus 18.13-s027_1 to get ChipTop.mapped.v. However, when I use Innovus v17.11-s080_1 and push ChipTop.mapped.v to the P&R flow, I am failed and I get an error prompted by Innovus and it says ERROR (NRIG-92) INSTANCE system/boom_tile/dcache/data/array_0_0/array_0_0_ext/mem_0_1 is not placed on the manufacturing grid. All instances must be legally placed. Correct placement before continuing. (In fact, mem_0_1 is SRAM2RW128x4)

I was wondering how I can push ChipTop.mapped.v together with sram_behav_models.v to the P&R flow?

Thank you very much!

Best regards,
Chen

[Jordan McGhee]

I am also seeing this exact same issue,

Has anyone been able to resolve this?

-Jordan

[Harrison Liew]

Jordan,

All SRAM instances must be placed within the design using `vlsi.inputs.placement_constraints`. The example in the repository is for the limited number of SRAMs in the TinyRocketConfig, but since you are using BOOM, there are many more SRAMs that need to be placed.

If you want early placement exploration in Innovus, you can set `par.innovus.floorplan_mode` to `auto`. This will invoke Innovus' auto-floorplanner, but note that your instances will not be placed optimally or cleanly (on the correct grid).

-Harrison

[Jordan McGhee]

Thank you Harrison,

Yes, after having placed the memory units down myself I was able to get it all working. Thank you so much for your time!

-Jordan

[Tianning Gao]

Hello Harrison,

The "defaults.yml" for Innovus said that we need a floorplan script if we want to set  "par.innovus.floorplan_mode" to "auto" (line 24 - 28 in /hammer-cadence-plugins/par/innovus/defaults.yml). Is there any guidence on how to write this script? Or we just need to give it a script file name?

Sincerely,

Tianning Gao

[Tianning Gao]

I just tried the "TinyRocketConfig" example that comes with chipyard. I removed all placement constraints for SRAMs and set "par.innovus.floorplan_mode: auto", but there were even more errors. Innovus now also failed to place some clock tree buffers. It failed to place only the SRAM blocks previously with floorplan_mode set to default.

Is there any other way to auto place the SRAMs (either with tool commands or external scripts)? 

I put the hammer configs and innovus logs here: https://drive.google.com/drive/folders/1myzTtrCUrXzdWXavFKnmWuzAEsvBTbBN?usp=sharing

Sincerely,

Tianning Gao

[Harrison Liew]

Tianning,

If you look at the implementation here, you'll see that "par.innovus.floorplan_mode: auto" calls the "plan_design" command in Innovus. If you want to use your own floorplanning script, you need to set the mode to "manual" and provide the path to the script in  "par.innovus.floorplan_script_contents".

We don't recommend using auto-floorplanning in general due to the fact that it causes lots of errors. Failure to place clock trees could be due to overlaps and impeded pin access by the auto-floorplanner. For now, you must place them all manually (after some hand calculation based on their size, which you can obtain from the LEF). We are working on a compiler that is derived from Chipyard aspects. Externally, macro placement is a huge area of research - see Google's Circuit Training and DREAMPlace for examples.

-Harrison

[Tianning Gao]

Got it. Thank you for the advice.

Sincerely,

Tianning Gao

[Tianning Gao]

Harrison, 

I'm now trying to manually place the SRAMs on a Small Boom chip, using the ASAP7 library. Can I have some more advice on how to estimate the spaceing value between

• SRAM and chip edge (assume there're chip pins on all four edges)?
• 2 SRAMs in one cache instance? 
• adjacent instances? E.g. i-cache and tage branch predictor bank

 

Sincerely,

Tianning Gao

[Harrison Liew]

Tianning,

1. You can estimate the number of pins on the edge that is adjacent to the SRAM edge. Then, calculate the number of routing tracks needed to route to those pins (across 2-3 layers). Add some overhead for power/clock and that should give you a minimum spacing.

2. Depends on how you abut them. If you put them back-to-back (pins facing left and right), then there's no required spacing between. If you place then with the pins facing inwards, then you need to calculate the # of wires (data in/out+address+overhead) of both SRAMs and that also gives you a minimum spacing.

3. This requires more thought. Since those two blocks are instruction-related, then it's likely you can place those SRAM arrays right next to each other. If they were not related, then you would place them farther away.

-Harrison

[Tianning Gao]

Harrison,

OK, I'll try calculate the spacing with some code. Thanks again.

Sincerely,

Tianning Gao