In testing out OpenROAD on MegaBoom, I would like to have a Verilog module that represents a BoomTile but with an asynchronous TileLink connection such that I can create a macro for this module and repeat it in a MegaBoom scenario with multiple BoomTiles.
The reason I want the asynchronous TileLink connection *inside* this macro, is that the BoomTile clock tree insertion latency is, even if quite deep, a concern that does not leak out of the macro.
TilePRCIDomain.sv, one is instantiated per BoomTile, almost fits the bill, except that the asynchronous clock crossing is on the *outside* of this module, in DigitalTop.
Sincerely,