RV32 Gemmini Config

Ahmet Oğuz Atlı

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Nov 12, 2020, 11:46:44 PM11/12/20

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Hello,

I am trying to bring up a Rocket SoC with Gemmini using Chipyard. My aim is to generate the smallest and lowest complexity SoC possible which can drive Gemmini and one more custom RoCC accelerator.

For this purpose, I am trying to create a configuration where I can have an RV32 Rocket and Gemmini, I remember from the ESSCIRC cooking session that generating such a model is possible. I have edited the GemminiRocketConfig to have the freechips.rocketchip.subsystem.WithRV32 fragment, but I get an unhelpful error message during elaboration.

[error] Bits.scala:160: Invalid bit range (31,32) in class chisel3.Bits
[error] Bits.scala:160: Invalid bit range (31,32) in class chisel3.Bits

This happens right after the Generated Address Map is printed. I also printed the full stack trace, but that was not very helpful either. The same error happens when I use a TinyCore, which also assumes RV32.

One more thing I've tried is to generate RV32 Rocket with Hwacha instead of Gemmini, and that elaborates successfully. Do you have an idea what might be going wrong?

I guess the more general form of my question would be the following: Do you have a sample configuration with minimal Rocket and peripherals and Gemmini? If not, any suggestions on which configuration fragments I should add or remove would also be very helpful.

Here is the configuration that I am trying to generate:

class GemminiRocketRV32Config extends Config(
new chipyard.iobinders.WithUARTAdapter ++
new chipyard.iobinders.WithTieOffInterrupts ++
new chipyard.iobinders.WithBlackBoxSimMem ++
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
new gemmini.DefaultGemminiConfig ++ // use Gemmini systolic array GEMM accelerator
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)

Jerry Zhao

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Nov 12, 2020, 11:48:11 PM11/12/20

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Can you post the entire error message?

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Ahmet Oğuz Atlı

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Nov 13, 2020, 1:51:29 PM11/13/20

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Here is the entire log:

OpenJDK 64-Bit Server VM warning: ignoring option MaxPermSize=256M; support was removed in 8.0

[info] Loading settings for project global-plugins from idea.sbt ...

[info] Loading global plugins from /afs/ece.cmu.edu/usr/aatli/.sbt/1.0/plugins

[info] Loading settings for project chipyard-build from plugins.sbt ...

[info] Loading project definition from /afs/ece.cmu.edu/project/km_group/.vol8/chipyard/project

[info] Loading settings for project chipyardRoot from build.sbt ...

[info] Loading settings for project barstoolsMacros from build.sbt ...

[info] Loading settings for project mdf from build.sbt ...

[info] Loading settings for project gemmini from build.sbt ...

[info] Loading settings for project ariane from build.sbt ...

[info] Loading settings for project boom from build.sbt ...

[info] Loading settings for project hwacha from build.sbt ...

[info] Loading settings for project icenet from build.sbt ...

[info] Loading settings for project testchipip from build.sbt ...

[info] Loading settings for project rocketConfig from build.sbt ...

[info] Loading settings for project hardfloat from build.sbt ...

[info] Loading settings for project chisel_testers from build.sbt ...

[info] Loading settings for project treadle from build.sbt ...

[info] Loading settings for project firrtl_interpreter from build.sbt ...

[info] Loading settings for project chisel from build.sbt ...

[info] Loading settings for project sim-build from plugins.sbt ...

[info] Loading project definition from /afs/ece.cmu.edu/project/km_group/.vol8/chipyard/sims/firesim/sim/project

[info] Loading settings for project firesim from build.sbt ...

[info] Loading settings for project midas from build.sbt ...

[info] Loading settings for project targetutils from build.sbt ...

[info] Resolving key references (32007 settings) ...

[info] Set current project to chipyardRoot (in build file:/afs/ece.cmu.edu/project/km_group/.vol8/chipyard/)

[info] Set current project to chipyard (in build file:/afs/ece.cmu.edu/project/km_group/.vol8/chipyard/)

[warn] Multiple main classes detected. Run 'show discoveredMainClasses' to see the list

[info] Compiling 1 Scala source to /afs/ece.cmu.edu/project/km_group/.vol8/chipyard/generators/rocket-chip/src/target/scala-2.12/classes ...

[warn] Multiple main classes detected. Run 'show discoveredMainClasses' to see the list

[info] Compiling 1 Scala source to /afs/ece.cmu.edu/project/km_group/.vol8/chipyard/generators/chipyard/target/scala-2.12/classes ...

[info] running chipyard.Generator --full-stacktrace --target-dir /afs/ece.cmu.edu/project/km_group/.vol8/chipyard/sims/vcs/generated-src/chipyard.TestHarness.GemminiRocketConfigCustom --name chipyard.TestHarness.GemminiRocketConfigCustom --top-module chipyard.TestHarness --legacy-configs chipyard.GemminiRocketConfigCustom

[info] [0.001] Elaborating design...

L2 InclusiveCache Client Map:

0 <= serial

1 <= stream-reader

2 <= stream-writer

3 <= Core 0 ICache

Interrupt map (1 harts 1 interrupts):

[1, 1] => uart_0

<stdin>:102.28-107.5: Warning (simple_bus_reg): /soc/subsystem_pbus_clock: missing or empty reg/ranges property

/dts-v1/;

/ {

#address-cells = <1>;

#size-cells = <1>;

compatible = "freechips,rocketchip-unknown-dev";

model = "freechips,rocketchip-unknown";

L19: aliases {

serial0 = &L15;

};

| => cL18: cpus {ompile / runMain 17s

#address-cells = <1>;

#size-cells = <0>;

L10: cpu@0 {

clock-frequency = <0>;

compatible = "sifive,rocket0", "riscv";

device_type = "cpu";

hardware-exec-breakpoint-count = <1>;

i-cache-block-size = <64>;

i-cache-sets = <64>;

i-cache-size = <4096>;

next-level-cache = <&L2>;

reg = <0x0>;

riscv,isa = "rv32imac";

riscv,pmpregions = <8>;

sifive,dtim = <&L9>;

status = "okay";

timebase-frequency = <1000000>;

L7: interrupt-controller {

#interrupt-cells = <1>;

compatible = "riscv,cpu-intc";

interrupt-controller;

};

L12: memory@80000000 {

device_type = "memory";

reg = <0x80000000 0x10000000>;

};

L17: soc {

#address-cells = <1>;

#size-cells = <1>;

compatible = "freechips,rocketchip-unknown-soc", "simple-bus";

ranges;

L2: cache-controller@2010000 {

cache-block-size = <64>;

cache-level = <2>;

cache-sets = <1024>;

cache-size = <524288>;

cache-unified;

compatible = "sifive,inclusivecache0", "cache";

next-level-cache = <&L12>;

reg = <0x2010000 0x1000>;

reg-names = "control";

sifive,mshr-count = <12>;

};

L4: clint@2000000 {

compatible = "riscv,clint0";

interrupts-extended = <&L7 3 &L7 7>;

reg = <0x2000000 0x10000>;

reg-names = "control";

};

L5: debug-controller@0 {

compatible = "sifive,debug-013", "riscv,debug-013";

debug-attach = "dmi";

interrupts-extended = <&L7 65535>;

reg = <0x0 0x1000>;

reg-names = "control";

};

L9: dtim@90000000 {

compatible = "sifive,dtim0";

reg = <0x90000000 0x4000>;

reg-names = "mem";

};

L1: error-device@3000 {

compatible = "sifive,error0";

reg = <0x3000 0x1000>;

};

L3: interrupt-controller@c000000 {

#interrupt-cells = <1>;

compatible = "riscv,plic0";

interrupt-controller;

interrupts-extended = <&L7 11>;

reg = <0xc000000 0x4000000>;

reg-names = "control";

riscv,max-priority = <1>;

riscv,ndev = <1>;

};

L14: rom@10000 {

compatible = "sifive,rom0";

reg = <0x10000 0x10000>;

reg-names = "mem";

};

L15: serial@54000000 {

clocks = <&L0>;

compatible = "sifive,uart0";

interrupt-parent = <&L3>;

interrupts = <1>;

reg = <0x54000000 0x1000>;

reg-names = "control";

};

L0: subsystem_pbus_clock {

#clock-cells = <0>;

clock-frequency = <100000000>;

clock-output-names = "subsystem_pbus_clock";

compatible = "fixed-clock";

};

Generated Address Map

0 - 1000 ARWX debug-controller@0

3000 - 4000 ARWX error-device@3000

10000 - 20000 R X rom@10000

2000000 - 2010000 ARW clint@2000000

2010000 - 2011000 ARW cache-controller@2010000

c000000 - 10000000 ARW interrupt-controller@c000000

54000000 - 54001000 ARW serial@54000000

80000000 - 90000000 ARWXC memory@80000000

90000000 - 90004000 ARWX dtim@90000000

[deprecated] Bits.scala:373 (79 calls): do_toBool is deprecated: "Use asBool instead"

[deprecated] Bits.scala:320 (1 calls): do_toBools is deprecated: "Use asBools instead"

[error] Bits.scala:160: Invalid bit range (31,32) in class chisel3.Bits

[warn] There were 2 deprecated function(s) used. These may stop compiling in a future release - you are encouraged to fix these issues.

[warn] Line numbers for deprecations reported by Chisel may be inaccurate; enable scalac compiler deprecation warnings via either of the following methods:

[warn] In the sbt interactive console, enter:

[warn] set scalacOptions in ThisBuild ++= Seq("-unchecked", "-deprecation")

[warn] or, in your build.sbt, add the line:

[warn] scalacOptions := Seq("-unchecked", "-deprecation")

[error] There were 2 error(s) during hardware elaboration.

[error] chisel3.internal.ChiselException: Fatal errors during hardware elaboration

[error] at chisel3.internal.throwException$.apply(Error.scala:85)

[error] at chisel3.internal.ErrorLog.checkpoint(Error.scala:152)

[error] at chisel3.internal.Builder$.$anonfun$build$1(Builder.scala:410)

[error] at scala.util.DynamicVariable.withValue(DynamicVariable.scala:62)

[error] at chisel3.internal.Builder$.build(Builder.scala:406)

[error] at chisel3.stage.ChiselGeneratorAnnotation.elaborate(ChiselAnnotations.scala:50)

[error] at chisel3.stage.phases.Elaborate.$anonfun$transform$1(Elaborate.scala:19)

[error] at scala.collection.TraversableLike.$anonfun$flatMap$1(TraversableLike.scala:245)

[error] at scala.collection.immutable.List.foreach(List.scala:392)

[error] at scala.collection.TraversableLike.flatMap(TraversableLike.scala:245)

[error] at scala.collection.TraversableLike.flatMap$(TraversableLike.scala:242)

[error] at scala.collection.immutable.List.flatMap(List.scala:355)

[error] at chisel3.stage.phases.Elaborate.transform(Elaborate.scala:18)

[error] at chisel3.stage.phases.Elaborate.transform(Elaborate.scala:16)

[error] at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:37)

[error] at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)

[error] at firrtl.options.Translator.transform(Phase.scala:240)

[error] at firrtl.options.Translator.transform$(Phase.scala:240)

[error] at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)

[error] at chisel3.stage.ChiselStage.$anonfun$run$2(ChiselStage.scala:35)

[error] at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:126)

[error] at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:122)

[error] at scala.collection.immutable.List.foldLeft(List.scala:89)

[error] at chisel3.stage.ChiselStage.run(ChiselStage.scala:35)

[error] at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)

[error] at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:37)

[error] at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)

[error] at firrtl.options.Translator.transform(Phase.scala:240)

[error] at firrtl.options.Translator.transform$(Phase.scala:240)

[error] at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)

[error] at firrtl.options.Stage.$anonfun$transform$5(Stage.scala:46)

[error] at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:126)

[error] at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:122)

[error] at scala.collection.immutable.List.foldLeft(List.scala:89)

[error] at firrtl.options.Stage.$anonfun$transform$3(Stage.scala:46)

[error] at logger.Logger$.$anonfun$makeScope$2(Logger.scala:168)

[error] at scala.util.DynamicVariable.withValue(DynamicVariable.scala:62)

[error] at logger.Logger$.makeScope(Logger.scala:166)

[error] at firrtl.options.Stage.transform(Stage.scala:46)

[error] at firrtl.options.Stage.execute(Stage.scala:57)

[error] at firrtl.options.StageMain.main(Stage.scala:69)

[error] at chipyard.Generator.main(Generator.scala)

[error] at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)

[error] at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62)

[error] at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)

[error] at java.lang.reflect.Method.invoke(Method.java:498)

[error] at sbt.Run.invokeMain(Run.scala:109)

[error] at sbt.Run.execute$1(Run.scala:79)

[error] at sbt.Run.$anonfun$runWithLoader$4(Run.scala:92)

[error] at scala.runtime.java8.JFunction0$mcV$sp.apply(JFunction0$mcV$sp.java:23)

[error] at sbt.util.InterfaceUtil$$anon$1.get(InterfaceUtil.scala:10)

[error] at sbt.TrapExit$App.run(TrapExit.scala:257)

[error] at java.lang.Thread.run(Thread.java:748)

Exception: sbt.TrapExitSecurityException thrown from the UncaughtExceptionHandler in thread "run-main-0"

[error] Nonzero exit code: 1

[error] (Compile / runMain) Nonzero exit code: 1

[error] Total time: 46 s, completed Nov 12, 2020 11:29:08 PM

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Ahmet Oğuz Atlı
Carnegie Mellon University | Electrical and Computer Engineering PhD Student

+1 (412) 758-8413 | aogu...@gmail.com

Jerry Zhao

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Nov 13, 2020, 2:48:58 PM11/13/20

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It appears Gemmini relies on 64-bit registers for passing commands to the accelerator. It is not compatible with a 32-bit host core.

We generally use a RV64GC rocket as the baseline core, as most software defaults to targeting RV64G.

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Ahmet Oğuz Atlı

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Nov 13, 2020, 10:56:11 PM11/13/20

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Thanks!

To view this discussion on the web visit https://groups.google.com/d/msgid/chipyard/CAC%2BpDSGBCZwF0FPQ_Tij-7g4J2U-mmF7jbL78yk8%3D79wo8NQSw%40mail.gmail.com.

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