Generating Verilog files from Config without the "make" flow

[Arka Maity]

Dear All,

I am new to Chipyard. I have a use case for self-learning, where I am trying to generate the RTL code from the following code snippet (without using the Chipyard's Make infrastructure).

class TinyRocketConfig extends Config(
  new chipyard.config.WithTLSerialLocation(
    freechips.rocketchip.subsystem.FBUS,
    freechips.rocketchip.subsystem.PBUS) ++                       // attach TL serial adapter to f/p busses
  new freechips.rocketchip.subsystem.WithNBanks(0) ++             // remove L2$
  new freechips.rocketchip.subsystem.WithNoMemPort ++             // remove backing memory
  new freechips.rocketchip.subsystem.With1TinyCore ++             // single tiny rocket-core
  new chipyard.config.AbstractConfig)

class HelloNewSoCSystem(implicit val param : Parameters) extends BaseSubsystem {
    override lazy val module = new HelloNewSoCSystemImp(_outer=this)
}

class HelloNewSoCSystemImp[+L <: HelloNewSoCSystem](_outer: HelloNewSoCSystem) extends BaseSubsystemModuleImp(_outer)

object HelloNewSoC extends App {
    implicit val param = new TinyRocketConfig
    (new ChiselStage).emitVerilog(LazyModule(new HelloNewSoCSystem()).module,Array("--target-dir","builds/TutorialGen"))
}

I get the following error message while executing the " HelloNewSoC" object. It appears that I am missing some clock connections, but I am not sure how can I add them. Also, I suspect that my definitions of HelloNewSoCSystemImp and HelloNewSoC are not correct.

[1007/1017] diplomatictester.compile
[info] compiling 1 Scala source to /home/amaity/Desktop/ChiselTutorial/playgroundAmaity/out/diplomatictester/compile/dest/classes ...
[info] done compiling
[1017/1017] diplomatictester.runMain
Exception in thread "main" java.lang.IllegalArgumentException: requirement failed: Diplomacy has detected a problem with your graph:
The following node appears left of a := 0 times and right of a := 1 times.
Either the number of bindings on both sides of the node match, or connect this node by left-hand side of :*= or right-hand side of :=*
ephemeral <localHelloNewSoC>.clock_sources node:
parents: <localHelloNewSoC>
locator:  (HelloNewSoC.scala:27:45)

​

Thanks

Arka