[Spike-as-a-tile] Verliator RTL simulation error with custom ISA

[Jongsang Yoo]

Hello!
I am currently experimenting with adding Custom ISA.

I modified the add of RV_I to create a custom ISA called mod and added it to riscv64-unknown-elf-gcc.

We also confirmed that the spoke simulator works normally by modifying the custom ISA called mod.

The above process was conducted by referring to the tutorial in this link

This code is the C code I compiled.

#include <stdio.h>

unsigned long read_cycles(void)

{

unsigned long cycles;

asm volatile ("rdcycle %0" : "=r" (cycles));

return cycles;

}

int main(){

unsigned long prev_cycle, current_cycle;

prev_cycle = read_cycles();

int a,b,c;

a = 5;

b = 2;

asm volatile

(

"mod %[z], %[x], %[y]\n\t"

: [z] "=r" (c)

: [x] "r" (a), [y] "r" (b)

);

if ( c != 1 ){

printf("\n[[FAILED]]\n");

return -1;

}

printf("\n[[PASSED]]\n");

current_cycle = read_cycles();

printf("Cycle : %ld\n", current_cycle - prev_cycle);

return 0;

}

The log is the terminal log which means normal operation.

Now I'm trying RTL-simulation with a berrillator using the spike-as-a-tile supported by chipyard.

However, the following error occurs.

[Log]

(/home/jongsang/chipyard/.conda-env) jongsang  ~/chipyard/sims/verilator  ↰ main  spike pk /home/jongsang/chipyard/tests/modISA_cycle.riscv

bbl loader

[[PASSED]]

Cycle : 43013

(/home/jongsang/chipyard/.conda-env) jongsang  ~/chipyard/sims/verilator  ↰ main  make CONFIG=SpikeConfig run-binary BINARY=/home/jongsang/chipyard/tests/modISA_cycle.riscv

Running with RISCV=/home/jongsang/chipyard/.conda-env/riscv-tools

if [ "/home/jongsang/chipyard/tests/modISA_cycle.riscv" != "none" ] && [ ! -f "/home/jongsang/chipyard/tests/modISA_cycle.riscv" ]; then printf "\n\nBinary /home/jongsang/chipyard/tests/modISA_cycle.riscv not found\n\n"; exit 1; fi

(set -o pipefail && /home/jongsang/chipyard/sims/verilator/simulator-chipyard.harness-SpikeConfig \

+permissive \

+dramsim +dramsim_ini_dir=/home/jongsang/chipyard/generators/testchipip/src/main/resources/dramsim2_ini +max-cycles=10000000 \

+verbose \

+permissive-off \

/home/jongsang/chipyard/tests/modISA_cycle.riscv \

\

</dev/null 2> >(spike-dasm > /home/jongsang/chipyard/sims/verilator/output/chipyard.harness.TestHarness.SpikeConfig/modISA_cycle.out) | tee /home/jongsang/chipyard/sims/verilator/output/chipyard.harness.TestHarness.SpikeConfig/modISA_cycle.log)

[UART] UART0 is here (stdin/stdout).

Constructing spike processor_t

Done constructing spike processor

[905000] %Error: TLMonitor_66.sv:316: Assertion failed in TOP.TestDriver.testHarness.ram.buffer.monitor: Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:76:45)

at Monitor.scala:45 assert(cond, message)

%Error: /home/jongsang/chipyard/sims/verilator/generated-src/chipyard.harness.TestHarness.SpikeConfig/gen-collateral/TLMonitor_66.sv:316: Verilog $stop

Aborting...

make: *** [/home/jongsang/chipyard/common.mk:325: /home/jongsang/chipyard/tests/modISA_cycle.riscv.run] Error 255

(/home/jongsang/chipyard/.conda-env) ✘ jongsang  ~/chipyard/sims/verilator  ↰ main 

[Rumi Naik]

Is there a wiki & tracker for these sorts of issues / workflows?

[Jerry Zhao]

The Github issues page for chipyard is the best place I think.

I must have missed this email. Assuming your modifications to spike do not cause any additional memory accesses, it is likely there is some code attempting to access inaccessible physical memory. If you send me a test case that breaks even without a custom Spike, I can try to look into it.

-Jerry

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[Fizza Haq]

Hello,
I am hitting the same TileLink assertion reported in this thread. I would like to emphasize that I have not made any modifications to Spike and I have not changed the Chipyard configuration in any way. I am running a standard Rocket Gemmini-based configuration as provided by Chipyard. All of my baremetal tests run successfully without any issues. The problem only appears when running Linux-based binaries using run-binary or run-binary-debug, where the simulation fails with the TileLink PutPartial assertion.  


(/home/fizza-haq/chipyard/.conda-env) fizza-haq@fizza-haq-VirtualBox:~/chipyard/sims/verilator$ make CONFIG=GemminiRocketConfig run-binary-debug BINARY=../../generators/gemmini/software/gemmini-rocc-tests/build/bareMetalC/matmul-linux
Running with RISCV=/home/fizza-haq/chipyard/.conda-env/riscv-tools
if [ "../../generators/gemmini/software/gemmini-rocc-tests/build/bareMetalC/matmul-linux" != "none" ] && [ ! -f "../../generators/gemmini/software/gemmini-rocc-tests/build/bareMetalC/matmul-linux" ]; then printf "\n\nBinary ../../generators/gemmini/software/gemmini-rocc-tests/build/bareMetalC/matmul-linux not found\n\n"; exit 1; fi
if [ "../../generators/gemmini/software/gemmini-rocc-tests/build/bareMetalC/matmul-linux" != "none" ]; then riscv64-unknown-elf-objdump -D -S ../../generators/gemmini/software/gemmini-rocc-tests/build/bareMetalC/matmul-linux > /home/fizza-haq/chipyard/sims/verilator/output/chipyard.harness.TestHarness.GemminiRocketConfig/matmul-linux.dump ; fi
(set -o pipefail &&  /home/fizza-haq/chipyard/sims/verilator/simulator-chipyard.harness-GemminiRocketConfig-debug \
+permissive \
+dramsim +dramsim_ini_dir=/home/fizza-haq/chipyard/generators/testchipip/src/main/resources/dramsim2_ini +max-cycles=10000000     \
+verbose \
+vcdfile=/home/fizza-haq/chipyard/sims/verilator/output/chipyard.harness.TestHarness.GemminiRocketConfig/matmul-linux.vcd \
+permissive-off \
../../generators/gemmini/software/gemmini-rocc-tests/build/bareMetalC/matmul-linux \
 \
</dev/null 2> >(spike-dasm > /home/fizza-haq/chipyard/sims/verilator/output/chipyard.harness.TestHarness.GemminiRocketConfig/matmul-linux.out) | tee /home/fizza-haq/chipyard/sims/verilator/output/chipyard.harness.TestHarness.GemminiRocketConfig/matmul-linux.log)
%Warning: System has stack size 8192 kb which may be too small; suggest 'ulimit -c 17347' or larger

[UART] UART0 is here (stdin/stdout).

[905000] %Error: TLMonitor_70.sv:298: Assertion failed in TOP.TestDriver.testHarness.ram.buffer.monitor: Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)

    at Monitor.scala:45 assert(cond, message)

%Error: /home/fizza-haq/chipyard/sims/verilator/generated-src/chipyard.harness.TestHarness.GemminiRocketConfig/gen-collateral/TLMonitor_70.sv:298: Verilog $stop
Aborting...
make: *** [/home/fizza-haq/chipyard/common.mk:350: ../../generators/gemmini/software/gemmini-rocc-tests/build/bareMetalC/matmul-linux.run.debug] Error 255