MegaBoom with OpenROAD, what should the .sdc file look like?

[Øyvind Harboe]

I have now built Verilog files to use with OpenROAD with:

make tutorial=sky130-openroad CONFIG=ChipLikeMegaBoomConfig buildfile

What should the .sdc file look like for the clocks at ChipTop?

There are three clocks in ChipTop https://github.com/The-OpenROAD-Project/megaboom/blob/931c2a882510bf5735dbf5efab1a8c474f838c49/mock/ChipTop.sv#L31

- "clock" - it looks like this can be on the order of 5000ps in OpenROAD.

- "serial_tl_0_clock" - 1000ps in OpenROAD seems to work...

- I had to mock the PLL by introducing a "fake_pll_clk" in ChipTop as Yosys couldn't compile the PLL

OpenROAD discussion: https://github.com/The-OpenROAD-Project/OpenROAD/discussions/4504

Modifications to Chipyard to build the above: https://groups.google.com/g/chipyard/c/BXsafsGlhJ0/m/lwUHEVGdAwAJ

Bazel layer on OpenROAD-flow-scripts tested with MegaBoom:

https://github.com/The-OpenROAD-Project/megaboom

The clock tree now looks much more promising, there is something strange going on on the right hand side though...

[Øyvind Harboe]

I ended up with something of the form, which worked quite well: https://github.com/The-OpenROAD-Project/OpenROAD/discussions/4522

set sdc_version 2.0

set clk_period 8500

set clk1_name  clock_uncore
create_clock -name $clk1_name -period $clk_period -waveform [list 0 [expr $clk_period/2]] [get_ports $clk1_name]
set_clock_uncertainty 10 [get_clocks $clk1_name]

set clk2_name  serial_tl_0_clock
create_clock -name $clk2_name -period $clk_period -waveform [list 0 [expr $clk_period/2]] [get_ports $clk2_name]
set_clock_uncertainty 10 [get_clocks $clk2_name]

set_clock_groups -asynchronous -group [get_clocks $clk1_name] -group [get_clocks $clk2_name]