Adding JTAG ports

[Seiji Munetoh]

Hi,

I'm looking at Chipyard v1.4 FPGA examples. Is there any example code to expose JTAG ports at TestHarness by using new shell?

Thanks!, -- Seiji

[James Dunn]

Hello Seiji,

Exposing JTAG ports to the harness is accomplished using IOBinders and HarnessBinders.

A simple example of this is how we exposed the JTAG ports to the Arty FPGA harness.

We use default (included in Chipyard) IOBinders to instantiate the JTAG IO cells and ports in the ChipTop layer. This is because there is nothing Arty-specific about the JTAG IO at the ChipTop layer that would require a custom IOBinder. This default JTAG IOBinder is located here. It is applied for designs that have the HasPeripheryDebug trait, which is the case for the Rocket config used for the Arty config.

However, a custom HarnessBinder is needed that connects the JTAG IO at the ChipTop layer to the Arty-specific harness IO. That HarnessBinder is here for Arty. Since the harness IOs represent physical pins on the Arty, we use an IOBUF construct (Xilinx IP which places a buffer) for the connection, as well as adding pullups as necessary for certain JTAG signals.

You should be able to follow a similar process for wiring up JTAG to any of the harnesses provided by fpga-shells.

Best,

James