Using UART in sifive-blocks

[정성준]

Hello, I'm implementing Rocket chip on FPGA without using freedom platform.

I have trouble using sifive UART.

I made Rocket core RTL with TLUART (baudrate = 115200) and connected uart_0_txd and uart_0_rxd to corresponding pins of FPGA.

And, I used the device tree generated with core RTL.

However, nothing shows during booting.

When I used Xilinx UART16550 ip instead of TLUART, I can see messages via UART.

Is there a way to get TLUART to work?

Thanks

[michael etzkorn]

Your flow looks a little interesting. Are you generating the design in sim and moving it into a harness manually? What are you using for bootup firmware? Is it still the chipyard fpga bootrom?  

One thing I could think of is you haven't enabled the TX and RX fifos. The Chipyard bootrom in the FPGA folder writes to tx_en, but the uart base address there is 0x6400_0000 not 0x5400_0000. I'm assuming you might be using a custom bootrom?

[정성준]

Are you generating the design in sim and moving it into a harness manually?

- Yes. I generate the design in sim and use ChipTop

What are you using for bootup firmware? Is it still the chipyard fpga bootrom?

- No, this design doesn't execute bootup firmware. It uses bootrom in rocket-chip directory. I thought what bootup firmware did was to copy bbl from SD card to memory.

One thing I could think of is you haven't enabled the TX and RX fifos. The Chipyard bootrom in the FPGA folder writes to tx_en, but the uart base address there is 0x6400_0000 not 0x5400_0000. I'm assuming you might be using a custom bootrom?

- I thought proxy kernel enables fifos...

2022년 3월 24일 목요일 오전 3시 47분 28초 UTC+9에 michael...@sage-micro.com님이 작성:

[michael etzkorn]

As I found out today, the harness binder for sim uses the UARTAdapter, this is different than the FPGA Harness Binder so this might have played into why your custom flow with the sim environment wasn't working. 

Or perhaps the PK isn't getting the proper device tree.