Porting the TinyRocketConfig on Arty-35

[Hadir Khan]

Hello,

I have ported the TinyRocketConfig design on the arty fpga using the make command shown in the "Prototyping flow" in the chipyard docs. However, looking at the schematic of the design, after running implementation in vivado, shows some pads left unconnected that may be used by the JTAG. I have attached the image of the schematic showing only the pins that are connected with the design.

I doubt that these connections are complete to connect JTAG and run bare-metal tests on top of the fpga board.

Any help regarding this matter?

[James Dunn]

Hello,

This looks correct to me. If you expand the IOBUF blocks in the schematic, it should clarify how it is working as a bidirectional buffer:

The "Overview of the IOBUF" section of this page explains further.

In the case of the signals you show, the IOBUF is used only as an input buffer, so the tristate control (T) is set high, making I a "don't care", and it is held low.

Regards,

James

[James Dunn]

I should add that these could be replaced with IBUFs and OBUFs, as the signals are unidirectional, but the connections were modeled after how SiFive's Freedom Arty wired things, which was using IOBUFs.

Regards,

James

[Hadir Khan]

Thanks for the timely response. Okay this makes sense to me now. I would need help in actually debugging the program over JTAG. I have burnt the bitstream of this design on the FPGA and connected the "Olimex ARM Tiny USB H" hardware adapter according to the "SiFive Freedom E30 Getting Started" guide. However, when I connect the riscv_openocd, there are certain errors that I am facing. This is described in detail here:
https://github.com/riscv/riscv-openocd/issues/581

I would greatly appreciate help in this matter.

Regards,
Hadir

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[James Dunn]

I replied in the issue. Since I can connect to the Arty by reproducing your steps, I don't think this is an issue with riscv-openocd, but some aspect of your Chipyard build, FTDI drivers, or connection between the Olimex debugger and Arty board.

Regards,

James

[Hadir Khan]

Thanks James for the response and various debugging steps. I will get back to you here with the steps you mentioned in the issue and provide you more information regarding the issue. By the way, I used the default ArtyTweakConfig, so the build must be fine as well since I did not change any defaults in the chipyard/fpga repository folder.

Regards,

Hadir

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[Hadir Khan]

Hi James,
Please see the latest development regarding the issue here: https://github.com/riscv/riscv-openocd/issues/581#issuecomment-778920804