SPI Flash File

[Edmund Leung]

Hey Chipyard community,

TL;DR - SPI Flash is looking for a file I don't have/don't know how to make

I built the standard SmallSPIFlashRocketConfig and LargeSPIFlashROMRocketConfig and simulated them using Verilator. I've successfully compiled and executed a baremetal executable to interact with UART0 in the RocketConfig build. Since the same UART module exists in the other builds at the same address, I expect them to behave almost exactly the same with the same executable as before. However, when I try to run the executable, I get an error. 

$ ./simulator-chipyard-SmallSPIFlashRocketConfig uart3.riscv 

This emulator compiled with JTAG Remote Bitbang client. To enable, use +jtag_rbb_enable=1.
Listening on port 43929
[UART] UART0 is here (stdin/stdout).
No memory image provided. Use +spiflash0=<file> to specify.
[0] %Error: plusarg_file_mem.sv:50: Assertion failed in TOP.TestHarness.spi_mem_0.memory
%Error: /mnt/data/chipyard/sims/verilator/generated-src/chipyard.TestHarness.SmallSPIFlashRocketConfig/plusarg_file_mem.sv:50: Verilog $stop
Aborting...
Aborted (core dumped)

I've tried to research different files I can input into it, but none seem to work. All the Chipyard documentation says under testchip IP is that the memory is backed by a file but no example file to use. I've tried the bootrom.rv64.img found in the testchipip repo, but that doesn't seem to work either. It throws the following error:

Error: image file mem_img.img is not large enough to store 0x10000 bytes.

I've also tried to write a file filled with all 0s or all 1s, but nothing seems to work. What kind of file is the SPI Flash looking for and where/how can I find one that works?

[Jerry Zhao]

Check chipyard/tests/spiflaah.py

Sorry this may not have been documented well. 

-Jerry

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[Edmund Leung]

TL;DR - generated spiflash.img file does not work

Here are the steps I took:

1. Rebuilt SmallSPIFlashRocketConfig build: make CONFIG=SmallSPIFlashRocketConfig

2. Generated .img file in chipyard/tests directory: make spiflash.img

3. Ran Verilator using my UART executable: ./simulator-chipyard-SmallSPIFlashRocketConfig +spiflash0=spiflash.img uart3.riscv

I get the following error:

This emulator compiled with JTAG Remote Bitbang client. To enable, use +jtag_rbb_enable=1.

Listening on port 33395

[UART] UART0 is here (stdin/stdout).

terminate called after throwing an instance of 'std::runtime_error'
  what():  could not open +spiflash0=spiflash.img (did you misspell it? If VCS, did you forget +permissive/+permissive-off?)

Based on spiflash.py, it looks like the script is writing meaningless data to the .img file and making it 1 MB in size. I honestly don't know if it needs meaningful data or a .img size that's at least 1 MB.

How can I load a memory image file that works?

[John Wright]

Hi Edmund,

1. The img file is just a binary file with the data you want to load onto the SPI flash model. It gets loaded into this model via a DPI call: https://github.com/ucb-bar/testchipip/blob/03535f56a6318236ab6abf5342d78eecf453984d/src/main/resources/testchipip/vsrc/SimSPIFlashModel.sv

2. +spiflash0=spiflash.img expects it to be in your run directory. You should use a relative path (see https://github.com/ucb-bar/chipyard/blob/main/.github/scripts/run-tests.sh)

John

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