How to create connection between two MMIO peripherals?

[s ren]

Hi all,

       I want to create connection between two MMIO peripherals, but I don't know how get their IO ports in top level. For example, one of the peripherals needs another peripheral's init_done signal to  update state.

        Below is a simple figure.

       

       device0  ----init_done---->   device1

            |                                               |

        ------------------------------------------------------ pbus 

Thanks in advance,

reny.

[michael etzkorn]

The general idea is connecting within digital top.

class MyDigitalTopModule[+L <: MyDigitalTop](l: L) extends MyChipyardSystemModule(l)
  with testchipip.CanHaveTraceIOModuleImp
  with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp
  with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp
  with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
  with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp
  with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp
  with sifive.blocks.devices.spi.HasPeripherySPIModuleImp
  with chipyard.example.CanHavePeripheryGCDModuleImp
  with HasDevice0ModuleImp
  with HasDevice1ModuleImp
  with freechips.rocketchip.util.DontTouch
{
  device1.io.init_done := device0.io.init_done
}

You can also combine traits if you don't plan to use these devices separately. 

You may have to return the module to a value to have it scoped within the DigitalTopModule class and if it's optional use map or foreach to unwrap the modules. 

[s ren]

Thanks you very much! This was exactly what I was looking for.