Question about building FPGA bitstream for VCU118

[Peng Xu]

Hi, chipyard community, 

Appreciate your help in advance.

I am running the make bitstream sample in chipyard doc (https://chipyard.readthedocs.io/en/stable/Prototyping/General.html#generating-a-bitstream) with this command "make SUB_PROJECT=vcu118 bitstream"

Firstly, I encountered this error, and it seems like the synth.tcl in chipyard/fpga/fpga-shells/xilinx/common/tcl cannot find the required IPs.

Then after editing the synth.tcl file by skipping the read IP process and rerun the command "make SUB_PROJECT=vcu118 bitstream", I encounter the following errors

The main error is module "vcu118mig" was not found.

After checking, "vcu118mig" is a IP defined in fpga-shells (chipyard/fpga/fpga-shells/src/main/scala/ip/xilinx/vcu118mig) and does not be generated successfully.

Is there any way to help me solve this problem?

Repository branches/tags I used:

chipyard, 117624d8eea27bafd613eec09e9b9b3e31239e08

gemmini, v0.6.4

fpga-shells, master

[Brendon Chetwynd]

One observation is that you are running as root.  You shouldn't have to do that for any chipyard build.  What version of Vivado are you using?

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[Peng Xu]

Yes, I am running as root. In fact, I build the chipyard environment in docker with ubuntu 20.04 image and run all the commands as root. I install the Vivado 2020.1 in host machine and map it into the docker container to use it.

[Peng Xu]

Can I know if there is any information on which command cannot be executed as root?