val slave: TLInwardNode =
(imp.slave
:= AXI4Buffer()
:= AXI4UserYanker()
:= AXI4Deinterleaver(p(CacheBlockBytes))
:= AXI4IdIndexer(idBits=c.sIDBits)
:= TLToAXI4(adapterName = Some("pcie-slave")))
val control: TLInwardNode =
(imp.control
:= AXI4Buffer()
:= AXI4UserYanker(capMaxFlight = Some(2))
:= TLToAXI4()
:= TLFragmenter(4, p(CacheBlockBytes), holdFirstDeny = true))
val master: TLOutwardNode =
(TLWidthWidget(c.busBytes)
:= AXI4ToTL()
:= AXI4UserYanker(capMaxFlight=Some(16))
:= AXI4Fragmenter()
:= AXI4IdIndexer(idBits=2)
:= imp.master)