Geting stuck in verilog generation from firrtl

[Eduardo Schwarz Danni]

Hi, I am trying to generate the verilog (and later run simulations) from my design, but I get stuck in the verilog generation.

When I run "make firrtl" it works, but "make verilog", "make", "make run-debug", etc do not.

The last message I get is "generators/chipyard/src/main/scala/harness/TestHarness.scala:19:7: note: For more information, see https://github.com/llvm/circt/issues/6970", what is just something from the makefile and does not relate to the problem. It prints that and stays there forever. The ammount of ram used after this point does not increase.

What I would like is some help to find the source of the problem, be it some flags or other methods to find out where it gets stuck and what is the source of the problem. I've tried averything I could find but nothing gives me more information.