CHIA: AI-driven co-design with Chipyard, FireSim, Hammer, and many other design flows

[Sagar Karandikar]

Hi Chipyard and FireSim community,

As you may have noticed, we are back to making regular releases of Chipyard and FireSim! Stay tuned for some cool new features.

We also recently launched CHIA (chialoops.ai, arxiv.org/abs/2606.27350), an open-source framework that makes it easy to design and deploy (at scale) all kinds of AI-driven HW/SW co-design flows, from agentic architectural discovery to automatically solving key chip engineering challenges with AI.

In CHIA, agentic AI-driven hardware and software design flows are expressed as CHIA loops: directed cyclic graphs whose nodes execute various system-on-chip design tools, microarchitectural simulators, software build systems, AI models, evolutionary coding agents, and more. Composing a CHIA loop is (almost) as easy as drawing an AI-infused design flow on a whiteboard!

The CHIA library provides node implementations for many popular tools, including Chipyard, Gem5, ChampSim, ESP, FireSim, Hammer (for commercial ASIC CAD tools), Vivado, AlphaEvolve, AdaEvolve, and many others.

Importantly, CHIA also provides a broad set of features to conduct principled science around the design of these AI-driven flows. These include isolation between AI models and hardware tools, enforcement of verification/validation, profiling mechanisms, fault-tolerant execution, and reliability at scale across 100s of heterogeneous systems (CPUs, FPGAs, GPUs, etc., across public cloud/on-prem.).

To showcase CHIA, we detail several example CHIA loops (all open-sourced!) in our arXiv paper and documentation:

1. Automatic, LLM-driven RTL implementation of microarchitectural features in an OOO superscalar RISC-V core (BOOM). We achieve substantial speedups (IPC and wallclock), validated by booting Linux and running all 25+ Trillion instructions of SPEC06 Ref, while meeting silicon area targets and having no critical path impact in both Sky130 and a commercial 16nm process.

2. Automatic, LLM-driven IPC-aware critical path optimization of BOOM. We achieve a nearly 2x wallclock speedup in the BOOM design booting Linux and running all 25+ Trillion instructions of SPEC06 Ref. This is achieved by agents automatically modifying the BOOM RTL to improve critical paths by 2x, while only compromising IPC by around 3%.

3. Automatic, LLM-driven generation of Gem5 microarchitectural models from the RISC-V BOOM RTL implementation.

4. Evolutionary architectural discovery.

5. Automatic, maintainer-friendly GitHub issue fixing.

Internally, we are using CHIA all over the place to compose, run, and share AI-driven design flows, and we will continue to open source new CHIA loops as we go. Like other projects from us in the past (Chipyard, FireSim, Hammer, etc.), we are planning to support CHIA in the open source indefinitely, and welcome your feedback and contributions!

Want to chat about CHIA? Reach out to me or any of my students leading the project: Angela Cui, Ferran Hermida Rivera, and Jack Toubes (all are in CC).

Learn more:
Web: chialoops.ai
Docs/Getting Started: docs.chialoops.ai
arXiv paper: arxiv.org/abs/2606.27350

Follow:
X: x.com/chialoop
Mailing List: https://groups.google.com/g/chialoops

Cheers,
Sagar

--
Sagar Karandikar
Assistant Professor
EECS, UC Berkeley
https://sagark.org

[Sagar Karandikar]

Oops, forgot +Angela Yue Cui +Ferran Hermida Rivera +Jack Toubes in CC. Feel free to reach out to us with any thoughts.

Thanks,

Sagar