Re: [chipyard] Rocket SoC Chip Boot Process

[Jerry Zhao]

The FPGA-softcore-running FESVR approach is not supported, or recommended. 

The intended approach is to use the FPGA as a lightweight shim between the test chip and the PC, where a host PC runs uart_tsi as the FESVR frontend, which communicates over UART to the FPGA, and then communicates over serial-TL to the test chip.

Look at the ChipLikeRocketConfig (example DUT) and the ChipBringupHostConfig (example FPGATop), along with the TetheredChipLikeRocketConfig (RTL sim of DUT + FPGATop).

The FPGATop is intended to be deployed on a FPGA through the fpga flow in chipyard. Currently Arty100T is supported, but VCU118 should be as well.

The binary loading procedure in FESVR writes the CLINT to send an interrupt to the core once the binary loading is complete.

-Jerry

On Mon, Jun 10, 2024 at 7:32 AM Yuan Dai <daiy...@gmail.com> wrote:

Hi,

I'm trying to tape out a Rocket SoC design and am facing challenges building a VCS simulation environment to boot the SoC.  According to 6.13. Chipyard Boot Process — Chipyard 1.11.0 documentation and 8.2. Communicating with the DUT — Chipyard 1.11.0 documentation ( if I've interpreted them correctly ), it seems that a feasible approach to boot the SoC is to build an FPGA-based RISC-V core to run the FESVR, then the core sends the program into the DRAM of SoC via Tilelink protocol? Therefore, I'm writing to inquire if there are any tutorials or examples available to guide me in building such a system. Additionally, I'm curious about how the SoC detects that the program has been successfully loaded into the DRAM and initiates execution under the current mechanism.

Thank you,

Yuan

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[Yuan Dai]

Hi Jerry,

Thanks for your response and guidance!

Best,

Yuan