Using SRAM Compiler to stub in Verilog models for synthesis

[Jay Patel]

Hello all

Due to my current configuration my memory complier is on a different machine than chipyard is, and there is no way to get access to the memory complier. 

With this said, I am having an increasingly diffcult time to use the hammer tool chain to stub in my generated memories into my rtl. 

I know I have to create a sram-cache.json to let hammer know about the srams I have to insert. However, I am unsure where to go from there with my current setup.