Building with SDL2

[hakam atassi]

Hello!

Hope you're well. I'm currently in the process of attempting to add an SDL2 window to the verilator simulation by including it as a black boxed MMIO periphiral what is essentially a memory mapped SRAM in much the same way as the GCD example. 

I know that my MMIO device works. I would now like to extend it to render an SDL2 frame through the DPI, using files "SDL2_frame.v" and "SDL2_frame.cc". Even the DPI integration works (clearing everything and doing a printf in the DPI function works fine) well until I run:

#include "SDL2/SDL.h", which, though on its own returns no errors, when I use SDL2 functions, I get "not defined" errors. When I then attempt to pass "EXTRA_SIM_LDFLAGS=-lSDL2" to the verilator sim, it seems to build fine, but fails on launch with the following error:

</dev/null 2> >(spike-dasm > /home/hakam/Repos/ChaosCore-chipyard/sims/verilator/output/chipyard.harness.TestHarness.RV32RocketConfig/rv32ui-p-add.out) | tee /home/hakam/Repos/ChaosCore-chipyard/sims/verilator/output/chipyard.harness.TestHarness.RV32RocketConfig/rv32ui-p-add.log)
/bin/bash: line 9: 514133 Aborted                 (core dumped) /home/hakam/Repos/ChaosCore-chipyard/sims/verilator/simulator-chipyard.harness-RV32RocketConfig-debug +permissive +dramsim +dramsim_ini_dir=/home/hakam/Repos/ChaosCore-chipyard/generators/testchipip/src/main/resources/dramsim2_ini +max-cycles=10000000 +loadmem=/home/hakam/Repos/ChaosCore-chipyard/toolchains/riscv-tools/ChaosCore-riscv-tests/isa/rv32ui-p-add +verbose +vcdfile=/home/hakam/Repos/ChaosCore-chipyard/sims/verilator/output/chipyard.harness.TestHarness.RV32RocketConfig/rv32ui-p-add.vcd +permissive-off /home/hakam/Repos/ChaosCore-chipyard/toolchains/riscv-tools/ChaosCore-riscv-tests/isa/rv32ui-p-add < /dev/null 2> >(spike-dasm > /home/hakam/Repos/ChaosCore-chipyard/sims/verilator/output/chipyard.harness.TestHarness.RV32RocketConfig/rv32ui-p-add.out)
     514134 Done                    | tee /home/hakam/Repos/ChaosCore-chipyard/sims/verilator/output/chipyard.harness.TestHarness.RV32RocketConfig/rv32ui-p-add.log

make: *** [/home/hakam/Repos/ChaosCore-chipyard/common.mk:348: /home/hakam/Repos/ChaosCore-chipyard/toolchains/riscv-tools/ChaosCore-riscv-tests/isa/rv32ui-p-add.run.debug] Error 134

I've attempted to add SDL2 to the conda env setup, even through it does seem to install it into the env, it, as mentioned, doesnt work.

So, my question is, how do I get a simulation to build when it requires something like SDL2? I must admit I am not an expert with these build flows, but considering that doing -lSDL2 worked locally but causes a seg fault in chipyard, I'm certainly missing something. Hoping there is a simple way of getting SDL2 to the build process for verilator. Please let me know. Thanks!

[hakam atassi]

I hope I am not getting ahead of my self here but I may have pinned down the issue. I noticed that running a very simple SDL2 sanity test in the top most directory of chipyard works fine in a new terminal if I dont source env, but breaks when I do source env, and doesnt un-break until I bring up a new terminal. Reverting back to an older version of SDL2 in the conda yaml file seems to have fixed the issue!