Uniquified IOCell problem

[Saltuk Akgül]

Hi everyone,
I am using GenericDigitalGPIOCell in my design to implement some inout ports. To be able to test it, I have to connect Analog() pad to another Analog()  port. Therefore, I put the same GenericDigitalGPIOCell to my adapter design in testbench. I use simulation with xcelium flow. The problem is, during compilation of verilog from scala it "uniquify" the io cells and turns them into GenericDigitalGPIOCell_TestHarness_UNIQUIFIED in Adapter.sv file. But I got this error with xcelium:


instance 'TestDriver.testHarness@TestHarness<module>.sim_0@Adapter<module>.test_set_of_tristate_buf_0' of design unit 'GenericDigitalGPIOCell_TestHarness_UNIQUIFIED' is unresolved in 'worklib.Adapter:sv'

In the generated file named IOCell_TestHarness_UNIQUIFIED.v, there is no module called GenericDigitalGPIOCell_TestHarness_UNIQUIFIED. I suspect that it has something to do with this terminal output:
sed -i s/"module IOCell"/"module IOCell_TestHarness_UNIQUIFIED"/ /home/user/chipyard/sims/xcelium/generated-src/chipyard.harness.TestHarness.PhyConfig/gen-collateral/IOCell_TestHarness_UNIQUIFIED.v

I worked around this problem by adding this line to chipyard/sims/xcelium/Makefile
sed -i 's/module GenericDigitalGPIOCell(/module GenericDigitalGPIOCell_TestHarness_UNIQUIFIED(/' $(GEN_COLLATERAL_DIR)/IOCell_TestHarness_UNIQUIFIED.v

My questions are:
1. Why this uniquify exist?
2. Is there a better way to fix this than my addition to Makefile

Thanks in advance
Saltuk

[Harrison Liew]

Saltuk,

It looks like the uniquification script we have is uniquifying the IOCell module in your TestHarness, even though it's from the same blackbox Verilog file.

To help us fix this bug, can you see if module GenericDigitalGPIOCell is declared in any other file in the generated-src/chipyard.harness.TestHarness.PhyConfig folder? My suspicion is that there is one that is used by the DUT's Verilog.

[Saltuk Akgül]

Hi,
When I search for module GenericDigitalGPIOCell,I get these declarations:

./chipyard.harness.TestHarness.PhyConfig.sfc.fir:                      extmodule GenericDigitalGPIOCell :
./gen-collateral/IOCell_TestHarness_UNIQUIFIED.v:                    module GenericDigitalGPIOCell(
./gen-collateral/extern_modules.sv:                                                // external module GenericDigitalGPIOCell
./gen-collateral/IOCell.v:                                                                   module GenericDigitalGPIOCell(
./chipyard.harness.TestHarness.PhyConfig.fir:                           extmodule GenericDigitalGPIOCell :

./chipyard.harness.TestHarness.PhyConfig.extra.anno.json:
./TestHarness.anno.json:
./chipyard.harness.TestHarness.PhyConfig.anno.json:
./chipyard.harness.TestHarness.PhyConfig.sfc.anno.json:
./chipyard.harness.TestHarness.PhyConfig.appended.anno.json:

This is before I manipulate IOCell_TestHarness_UNIQUIFIED.v with a command in Makefile
I hope this helps.
Saltuk

15 Eylül 2023 Cuma tarihinde saat 01:25:56 UTC+2 itibarıyla harris...@berkeley.edu şunları yazdı: