Copying Generated Verilog and TCL scripts to Windows for Vivado

[Gabe R]

Hi all,

I'm trying to learn how to use chipyard, and to generate some designs to run on an FPGA. Unfortunately, I don't have a Linux system available, so I've had to fall back to using a docker container to run chipyard (conda did not seem to be working for me on WSL). 

I managed to get everything set up, and I tried to run one of the demos with  make SUB_PROJECT=nexysvideo verilog hoping that I could then copy the generated verilog to Windows, and import it into Vivado. 

Unfortunately, it seems that there are some components that are not generated, and expect to run TCL scripts with Vivado (I'm guessing to use Xilinx IP, and create the Vivado project itself). Is there a guide on which files I would need to copy over and manually run to finalize everything for creating a Vivado on a Windows computer, rather than just relying on make bitstream? 

Gabe