Problems with verilog generation

[Eduardo Schwarz Danni]

Hi, 

I've created a design that is a modification of the BOOM, and when trying to generate the verilog from the chisel code I get stuck. Some of the modifications work and some not, and I'm trying to find the problem.

With the problematic one running "make firrtl" works, but running "make verilog" does not, and the last message I get is "generators/chipyard/src/main/scala/harness/TestHarness.scala:19:7: note: For more information, see https://github.com/llvm/circt/issues/6970", what is likely not related to the problem, and only the last thing that is successfully printed. After this message nothing happens, and no matter how much time I wait it does not go further with the verilog generation.

I've tries many different combinations of flags, but none gives me more information on where exactly I'm stuck and what may be the cause of it. 

What I wanted for help is ideas to how to get more informtation from the firrtl, to know exactly where it does get stuck and if possible doing what.