Rocket SoC Boot Process

[Yuan Dai]

Hi,
I'm trying to tape out a Rocket SoC integrated with our custom accelerator. Our design utilizes a 40nm technology node, and we have specific technology-related components including I/O pads, compiled memory blocks, PLL IP, and a DDR controller IP.  

Since this is our first tape-out, I have several questions that I would like to ask:

1. Since we have difficulty using Hammer, we replace the memory block in Chipyard's generated RTL with the compiled memory blocks and connect the DigitalTop to the PLL and I/O pads.  I'm curious to know if this approach is feasible and if there are any potential issues we should be aware of.
2. From my understanding of the documentation on Adding Memory Blocks Generated By Foundry Compiler and  Arty100T board + TSI-over-UART, it seems a feasible way to boot the chip is using an Arty FPGA, which serves as a bridge between the CPU and the chip. More specifically, using the Arty FPGA transmits the binary data from the CPU (via UART) to the chip (via serial tilelink).  Could you please confirm if my interpretation is correct?

I appreciate your support and guidance！

Thanks & Regards,

Yuan

[Jerry Zhao]

1. Yes this is feasible. The only challenge is that Chipyard's RTL simulations will not capture the functional behavior of the PLL/IOCells/etc, since they all exist outside of chipyard. If you want to perform RTL, post-syn, or post-par simulation of your complete system, you'll have to set that up on your own.
2. Yes. That is correct. uart_tsi sends TSI packets encoded as UART to the FPGA. The FPGA decodes the TSI packets, converts them to TileLink, then sends them as serial-TL to the DUT. In principle, another approach could be to send TSI-encoded-as-UART directly to the chip through a UARTTSI receiver on the chip, bypassing the need for a FPGA entirely. For this to work, the UART on the chip must be running at a known fixed frequency during the entire process. Having a FPGA is also generally useful for bringup, so the no-FPGA-bringup flow hasn't been developed deeply.

-Jerry

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[Yuan Dai]

Hi Jerry,

Thanks for your response.  My questions have been resolved.

Yuan

[Yuan Dai]

Hi Jerry,

I think I misunderstood the document on the Arty100T board + TSI-over-UART. I used to think that the ARTY-100T project with Chipyard had implemented the process of "UART -> TileLink." However, when I ran the ARTY-100T project recently, I found that the project demonstrated that we could bringup a chip by the "TSI-over-UART" method instead of building the bridge between the Host and test chip. I am trying to figure out whether my understanding is correct. If so, I have a question: "Do I need to build such a "bridge" by myself?" More specifically, since our chip has its own DRAM, we need to use an FPGA to implement the process of "TSI-over-UART".

I am looking forward to your guidance.

Thanks & Regards,

Yuan

在2024年6月12日星期三 UTC+8 00:58:39<jerr...@berkeley.edu> 写道：

[Jerry Zhao]

The UART used for TSI-over-UART on the default Arty100T config is not the normal memory-mapped UART peripheral... rather, this configuration connects a custom device to the UART pins that converts between UART and TSI.

If the chip you are trying to bring up also connected its UART pins to a UARTToTSI device, then yes, technically you do not need a "bridge" FPGA. This is not the default configuration, however.

-Jerry

To view this discussion on the web visit https://groups.google.com/d/msgid/chipyard/5852c250-398b-4cd4-888e-31cf88bb79fan%40googlegroups.com.

[Yuan Dai]

Hi Jerry,

Thanks for your response.

My questions are solved, and I will learn more about this.

Regards,

Yuan