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Mar 12

Newbie Question - Version control of custom project

Hi, I am just starting to look at Chipyard, I am particularly interested in generating a 2 core

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Newbie Question - Version control of custom project

Hi, I am just starting to look at Chipyard, I am particularly interested in generating a 2 core

Mar 12

Mar 12

Chipyard setup failing

Hi all, I am trying to setup a Chipyard environment on my Ubuntu 22.04 LTS machine and I am getting

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Chipyard setup failing

Hi all, I am trying to setup a Chipyard environment on my Ubuntu 22.04 LTS machine and I am getting

Mar 12

Mar 12

Follow-up on a recent Chipyard bug report

Hi Chipyard maintainers, I am writing to politely follow up on an issue I recently submitted to the

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Follow-up on a recent Chipyard bug report

Hi Chipyard maintainers, I am writing to politely follow up on an issue I recently submitted to the

Mar 12

Yashwant Kumar Balivada

Mar 8

Query regarding Inclusive Cache in the abstract configuration

Hello, I am currently working on integrating a prefetcher into the BOOM core. In the abstract

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Query regarding Inclusive Cache in the abstract configuration

Hello, I am currently working on integrating a prefetcher into the BOOM core. In the abstract

Mar 8

Navyasree Kukatlapalli

Mar 3

CoreMark performance drop with vector enabled on Saturn core (Rocket & Shuttle)

Hi, I am Navya. I am currently running CoreMark on the Saturn core with both Rocket and Shuttle

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CoreMark performance drop with vector enabled on Saturn core (Rocket & Shuttle)

Hi, I am Navya. I am currently running CoreMark on the Saturn core with both Rocket and Shuttle

Mar 3

Feb 16

Genus synth of CVA6: empty module + feed-through/unloaded warnings — expected?

Hi everyone — quick question about synthesizing CVA6 with Cadence Genus. I'm running synthesis

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Genus synth of CVA6: empty module + feed-through/unloaded warnings — expected?

Hi everyone — quick question about synthesizing CVA6 with Cadence Genus. I'm running synthesis

Feb 16

Fizza Haq, Hasan Nazim Genc2

Jan 26

Understanding Gemmini’s Uncached TileLink Path and L1/L2 Coherence Implications

Hi Fizza, Sorry for the late reply. This is my understanding of how Gemmini interacts with TileLink

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Understanding Gemmini’s Uncached TileLink Path and L1/L2 Coherence Implications

Hi Fizza, Sorry for the late reply. This is my understanding of how Gemmini interacts with TileLink

Jan 26

Vincent Ulitzsch, Junaid amjad2

Jan 14

How can I change BOOM's reset vector to at address 0x80000000?

The final address for bootrom is decided by class WithBootROM (generators/chipyard/src/main/scala/

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How can I change BOOM's reset vector to at address 0x80000000?

The final address for bootrom is decided by class WithBootROM (generators/chipyard/src/main/scala/

Jan 14

Varun Somashekar

Jan 13

SRAM issues with sky130 Rocket Core Bring-Up

Hello, I am with a group at my university evaluating the Rocket Core for our project. We are running

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SRAM issues with sky130 Rocket Core Bring-Up

Hello, I am with a group at my university evaluating the Rocket Core for our project. We are running

Jan 13

Jan 1

Is there any LLM/SLLM demo running with gemmini and RVV?

Hi, Just as mentioned , Is there any LLM/SLLM demo running with gemmini and RVV? I think this is an

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Is there any LLM/SLLM demo running with gemmini and RVV?

Hi, Just as mentioned , Is there any LLM/SLLM demo running with gemmini and RVV? I think this is an

Jan 1

Musa Kartal Engin

12/24/25

Issues running UART TSI on Nexys Video with GemminiNoDDR15MHzNexysVideoConfig - Stuck at "Wrote 0"

Soru İçeriği (Body): Hi everyone, I'm trying to bring up Gemmini on a Nexys Video board using the

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Issues running UART TSI on Nexys Video with GemminiNoDDR15MHzNexysVideoConfig - Stuck at "Wrote 0"

Soru İçeriği (Body): Hi everyone, I'm trying to bring up Gemmini on a Nexys Video board using the

12/24/25

Tatsuya, … Ashbin Shiju10

12/18/25

How to Implement Custom IP Core?

To add Custom Core into Chipyard : in the chipyard/generators/mytile/src/main/resources/vsrc add the

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How to Implement Custom IP Core?

To add Custom Core into Chipyard : in the chipyard/generators/mytile/src/main/resources/vsrc add the

12/18/25

Jongsang Yoo, … Fizza Haq4

12/17/25

[Spike-as-a-tile] Verliator RTL simulation error with custom ISA

Hello, I am hitting the same TileLink assertion reported in this thread. I would like to emphasize

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[Spike-as-a-tile] Verliator RTL simulation error with custom ISA

Hello, I am hitting the same TileLink assertion reported in this thread. I would like to emphasize

12/17/25

Maria Jose Belda Beneyto, … Tianhao Cai7

12/8/25

Gemmini design doesn't fit on instance target

Dear MªJosé, Thinh, From my previous experience, FP units are very LUTs-costly. You can try to use

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Gemmini design doesn't fit on instance target

Dear MªJosé, Thinh, From my previous experience, FP units are very LUTs-costly. You can try to use

12/8/25

Eduardo Schwarz Danni

12/6/25

Geting stuck in verilog generation from firrtl

Hi, I am trying to generate the verilog (and later run simulations) from my design, but I get stuck

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Geting stuck in verilog generation from firrtl

Hi, I am trying to generate the verilog (and later run simulations) from my design, but I get stuck

12/6/25

Eduardo Schwarz Danni

12/6/25

Problems with verilog generation

Hi, I've created a design that is a modification of the BOOM, and when trying to generate the

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Problems with verilog generation

Hi, I've created a design that is a modification of the BOOM, and when trying to generate the

12/6/25

12/1/25

Issue setting up riscv-tools

Hi, I get the following error when I try to set up Chipyard on my local machine with riscv-tools:

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Issue setting up riscv-tools

Hi, I get the following error when I try to set up Chipyard on my local machine with riscv-tools:

12/1/25

陳冠穎, … Ranjith Kumar5

12/1/25

Is there any possibility to run generated SoC on Xilinx Alveo U50 or U55c?

Hi, Can you brief the method you have followed to successfully program the zcu102 using chipyard

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Is there any possibility to run generated SoC on Xilinx Alveo U50 or U55c?

Hi, Can you brief the method you have followed to successfully program the zcu102 using chipyard

12/1/25

11/20/25

Saturn VPU cycle counter

Hello I'm trying to check the cycle count in Saturn VPU(+Rocket core) using Verilator. My

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Saturn VPU cycle counter

Hello I'm trying to check the cycle count in Saturn VPU(+Rocket core) using Verilator. My

11/20/25

11/17/25

Chipyard with Xilinx KC705 board

Dear all, I am new to Chipyard and my group wants to implement Rocket and BOOM cores on KC705 because

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Chipyard with Xilinx KC705 board

Dear all, I am new to Chipyard and my group wants to implement Rocket and BOOM cores on KC705 because

11/17/25

11/10/25

How can I invoke a RoCC accelerator to execute a program on a FireMarshal system?

In the following configuration (where an additional Tweaks has been added to the FPGA), programs

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How can I invoke a RoCC accelerator to execute a program on a FireMarshal system?

In the following configuration (where an additional Tweaks has been added to the FPGA), programs

11/10/25

11/10/25

how can i use rocc accelerator run accum.riscv and charcount.riscv on firemarshal linux

I modified vcu118 to deploy on zcu102, and successfully ran firemarshal linux on it. I wrote a "

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how can i use rocc accelerator run accum.riscv and charcount.riscv on firemarshal linux

I modified vcu118 to deploy on zcu102, and successfully ran firemarshal linux on it. I wrote a "

11/10/25

10/18/25

Xcelium reported multiple "Unknown option *** "

I'm using hammer under directory "chipyard/vlsi". The OS is CentOS 7.9. Xcelium version

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Xcelium reported multiple "Unknown option *** "

I'm using hammer under directory "chipyard/vlsi". The OS is CentOS 7.9. Xcelium version

10/18/25

shravan ramesh, Junaid amjad2

9/30/25

issue on scripts

This is definitely some env issue. Seems like you are using some older version of chipyard, switch to

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issue on scripts

This is definitely some env issue. Seems like you are using some older version of chipyard, switch to

9/30/25

이신우 / 학생 / 전기·정보공학부, Matthew Edwin Weingarten2

9/30/25

Generating firrtl IR with Top circuit as RocketTile

Hi, Can you give more insight into what you will do with the generated firrtl IR? Are you using CIRCT

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Generating firrtl IR with Top circuit as RocketTile

Hi, Can you give more insight into what you will do with the generated firrtl IR? Are you using CIRCT

9/30/25

Jerry Ho, … Scott Eckart6

9/23/25

Best Practice of witing bootrom for chipyard based ASIC design

Hi Jerry, Not sure if you'll see this (being that this thread is now a year old) - but any help

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Best Practice of witing bootrom for chipyard based ASIC design

Hi Jerry, Not sure if you'll see this (being that this thread is now a year old) - but any help

9/23/25

thh, Học Nguyễn Hữu2

9/23/25

Generate bitstream for only NoC-Standalone config

Hi there, I'm fourth grade of UIT-HCM, I have the same project topic as your (maybe). If you are

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Generate bitstream for only NoC-Standalone config

Hi there, I'm fourth grade of UIT-HCM, I have the same project topic as your (maybe). If you are

9/23/25

이신우 / 학생 / 전기·정보공학부

9/23/25

Generating RocketTIle firrtl IR

Hello, I am an undergraduate student studying RocketChip Generator. I am having a hard time

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Generating RocketTIle firrtl IR

Hello, I am an undergraduate student studying RocketChip Generator. I am having a hard time

9/23/25

9/23/25

[Chipyard/Gemmini] Simulation Fails with "ReservationStation.scala" Assertion for Softmax/Layernorm Workloads

Hello Chipyard Developers and Community, I am encountering a simulation assertion failure when

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[Chipyard/Gemmini] Simulation Fails with "ReservationStation.scala" Assertion for Softmax/Layernorm Workloads

Hello Chipyard Developers and Community, I am encountering a simulation assertion failure when

9/23/25

9/23/25

Using SRAM Compiler to stub in Verilog models for synthesis

Hello all Due to my current configuration my memory complier is on a different machine than chipyard

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Using SRAM Compiler to stub in Verilog models for synthesis

Hello all Due to my current configuration my memory complier is on a different machine than chipyard

9/23/25

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