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Omar Shah
Dec 1
Issue setting up riscv-tools
Hi, I get the following error when I try to set up Chipyard on my local machine with riscv-tools:
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Issue setting up riscv-tools
Hi, I get the following error when I try to set up Chipyard on my local machine with riscv-tools:
Dec 1
陳冠穎
, …
Ranjith Kumar
5
Dec 1
Is there any possibility to run generated SoC on Xilinx Alveo U50 or U55c?
Hi, Can you brief the method you have followed to successfully program the zcu102 using chipyard
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Is there any possibility to run generated SoC on Xilinx Alveo U50 or U55c?
Hi, Can you brief the method you have followed to successfully program the zcu102 using chipyard
Dec 1
강준석
Nov 20
Saturn VPU cycle counter
Hello I'm trying to check the cycle count in Saturn VPU(+Rocket core) using Verilator. My
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Saturn VPU cycle counter
Hello I'm trying to check the cycle count in Saturn VPU(+Rocket core) using Verilator. My
Nov 20
Fizza Haq
Nov 18
Understanding Gemmini’s Uncached TileLink Path and L1/L2 Coherence Implications
Hi everyone, I'm trying to better understand how TileLink behaves in Chipyard specifically when
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Understanding Gemmini’s Uncached TileLink Path and L1/L2 Coherence Implications
Hi everyone, I'm trying to better understand how TileLink behaves in Chipyard specifically when
Nov 18
MA Qureshi
Nov 17
Chipyard with Xilinx KC705 board
Dear all, I am new to Chipyard and my group wants to implement Rocket and BOOM cores on KC705 because
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Chipyard with Xilinx KC705 board
Dear all, I am new to Chipyard and my group wants to implement Rocket and BOOM cores on KC705 because
Nov 17
Someone Pu
Nov 10
How can I invoke a RoCC accelerator to execute a program on a FireMarshal system?
In the following configuration (where an additional Tweaks has been added to the FPGA), programs
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How can I invoke a RoCC accelerator to execute a program on a FireMarshal system?
In the following configuration (where an additional Tweaks has been added to the FPGA), programs
Nov 10
Someone Pu
Nov 10
how can i use rocc accelerator run accum.riscv and charcount.riscv on firemarshal linux
I modified vcu118 to deploy on zcu102, and successfully ran firemarshal linux on it. I wrote a "
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how can i use rocc accelerator run accum.riscv and charcount.riscv on firemarshal linux
I modified vcu118 to deploy on zcu102, and successfully ran firemarshal linux on it. I wrote a "
Nov 10
Tianning Gao
Oct 18
Xcelium reported multiple "Unknown option *** "
I'm using hammer under directory "chipyard/vlsi". The OS is CentOS 7.9. Xcelium version
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Xcelium reported multiple "Unknown option *** "
I'm using hammer under directory "chipyard/vlsi". The OS is CentOS 7.9. Xcelium version
Oct 18
shravan ramesh
,
Junaid amjad
2
Sep 30
issue on scripts
This is definitely some env issue. Seems like you are using some older version of chipyard, switch to
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issue on scripts
This is definitely some env issue. Seems like you are using some older version of chipyard, switch to
Sep 30
이신우 / 학생 / 전기·정보공학부
,
Matthew Edwin Weingarten
2
Sep 30
Generating firrtl IR with Top circuit as RocketTile
Hi, Can you give more insight into what you will do with the generated firrtl IR? Are you using CIRCT
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Generating firrtl IR with Top circuit as RocketTile
Hi, Can you give more insight into what you will do with the generated firrtl IR? Are you using CIRCT
Sep 30
Jerry Ho
, …
Scott Eckart
6
Sep 23
Best Practice of witing bootrom for chipyard based ASIC design
Hi Jerry, Not sure if you'll see this (being that this thread is now a year old) - but any help
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Best Practice of witing bootrom for chipyard based ASIC design
Hi Jerry, Not sure if you'll see this (being that this thread is now a year old) - but any help
Sep 23
thh
,
Học Nguyễn Hữu
2
Sep 23
Generate bitstream for only NoC-Standalone config
Hi there, I'm fourth grade of UIT-HCM, I have the same project topic as your (maybe). If you are
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Generate bitstream for only NoC-Standalone config
Hi there, I'm fourth grade of UIT-HCM, I have the same project topic as your (maybe). If you are
Sep 23
이신우 / 학생 / 전기·정보공학부
Sep 23
Generating RocketTIle firrtl IR
Hello, I am an undergraduate student studying RocketChip Generator. I am having a hard time
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Generating RocketTIle firrtl IR
Hello, I am an undergraduate student studying RocketChip Generator. I am having a hard time
Sep 23
贾名震
2
Sep 23
[Chipyard/Gemmini] Simulation Fails with "ReservationStation.scala" Assertion for Softmax/Layernorm Workloads
Hello Chipyard Developers and Community, I am encountering a simulation assertion failure when
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[Chipyard/Gemmini] Simulation Fails with "ReservationStation.scala" Assertion for Softmax/Layernorm Workloads
Hello Chipyard Developers and Community, I am encountering a simulation assertion failure when
Sep 23
Jay Patel
Sep 23
Using SRAM Compiler to stub in Verilog models for synthesis
Hello all Due to my current configuration my memory complier is on a different machine than chipyard
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Using SRAM Compiler to stub in Verilog models for synthesis
Hello all Due to my current configuration my memory complier is on a different machine than chipyard
Sep 23
Cole Strickler
Sep 8
Marking DRAM Region uncacheable
Hello, I am looking to treat a region of DRAM as uncacheable. I am using the FASED model. I basically
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Marking DRAM Region uncacheable
Hello, I am looking to treat a region of DRAM as uncacheable. I am using the FASED model. I basically
Sep 8
Lucas Arruk
,
Junaid amjad
2
Aug 30
Issue on running CoreMark bare-metal on RocketCore
Hi, I ran the same test with the default rocket config and it's working fine. Well it did not
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Issue on running CoreMark bare-metal on RocketCore
Hi, I ran the same test with the default rocket config and it's working fine. Well it did not
Aug 30
John Charlie
,
Junaid amjad
2
Aug 30
Any Documentation about SoC registers in default Chipyard configurations?
Hi, There is not such a datasheet or something, but we do get .json files listing all memory mapped
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Any Documentation about SoC registers in default Chipyard configurations?
Hi, There is not such a datasheet or something, but we do get .json files listing all memory mapped
Aug 30
Nico Röder
Aug 29
SD card becomes slower after booting Firemarshal image
After booting buildroot successfully with an SD card speed of 25MHz, reading data from the second
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SD card becomes slower after booting Firemarshal image
After booting buildroot successfully with an SD card speed of 25MHz, reading data from the second
Aug 29
Kelly Xu
,
Junaid amjad
5
Aug 25
Swapping ROM and DRAM addresses - Sodor Core
Thank you, this worked! On Monday, August 25, 2025 at 12:17:45 PM UTC-4 junaida...@gmail.com wrote:
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Swapping ROM and DRAM addresses - Sodor Core
Thank you, this worked! On Monday, August 25, 2025 at 12:17:45 PM UTC-4 junaida...@gmail.com wrote:
Aug 25
Nick Lee
, …
jinhui pan
5
Jul 7
FPGA prototyping: cannot detect sd card 2nd partition
I have same problem also. Please contact me if someone have solved this problem. I add CONFIG_MMC=y,
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FPGA prototyping: cannot detect sd card 2nd partition
I have same problem also. Please contact me if someone have solved this problem. I add CONFIG_MMC=y,
Jul 7
edward mulier
,
Tung Hoang
2
Jul 1
Area of 16bit floating-point Gemmini
Table 3 of the below paper has MAC int8 and fp16 area https://arxiv.org/pdf/1811.01721 On Tue, Jul 1,
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Area of 16bit floating-point Gemmini
Table 3 of the below paper has MAC int8 and fp16 area https://arxiv.org/pdf/1811.01721 On Tue, Jul 1,
Jul 1
bizhao shi
Jul 1
How to enable more than foure RoCC accelerators within one core?
Dear authors, I am a beginner with Chipyard, and I am curious about the RoCC extension. Here are some
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How to enable more than foure RoCC accelerators within one core?
Dear authors, I am a beginner with Chipyard, and I am curious about the RoCC extension. Here are some
Jul 1
Yuval Mandel
Jul 1
Issues generating verilator waveforms .vcd files with chipyard
I have been making a medium boom processor using an existing config without alterations with the line
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Issues generating verilator waveforms .vcd files with chipyard
I have been making a medium boom processor using an existing config without alterations with the line
Jul 1
ahmad othman
Jun 26
Login Issue on VCU118 Firemarshal Image – Password Not Accepted
After building the Firemarshal image for the VCU118 board according to the official tutorial, the
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Login Issue on VCU118 Firemarshal Image – Password Not Accepted
After building the Firemarshal image for the VCU118 board according to the official tutorial, the
Jun 26
amoon_ea
Jun 11
Problem with Tilelink protocol handshake between Rocket Core and a MMIO device
I am trying to add a MMIO device to rocket-chip in chipyard and I want to use Tilelink interface.
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Problem with Tilelink protocol handshake between Rocket Core and a MMIO device
I am trying to add a MMIO device to rocket-chip in chipyard and I want to use Tilelink interface.
Jun 11
George Anagnostopoulos
,
Noah Limpert
2
Jun 5
IP: Socket: Function Not Implemented
Hi George, did you ever resolve this issue? I am trying to do some communication between the host and
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IP: Socket: Function Not Implemented
Hi George, did you ever resolve this issue? I am trying to do some communication between the host and
Jun 5
Nure Tanjim
, …
yj Han
3
Jun 4
Skipping Conda Initialization & Setting up RISCV Variable
You can try deleting the .conda-lock-env directory and then re-running the installation script. 在2025
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Skipping Conda Initialization & Setting up RISCV Variable
You can try deleting the .conda-lock-env directory and then re-running the installation script. 在2025
Jun 4
韩丰泽
, …
Jerry Zhao
4
Jun 3
chipyard vcu118 prototype & linux boot continuously failed
Would you be able to PR the fix? On Tue, Jun 3, 2025 at 11:33 Amirmohammad Nazari <amirmohammad.
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chipyard vcu118 prototype & linux boot continuously failed
Would you be able to PR the fix? On Tue, Jun 3, 2025 at 11:33 Amirmohammad Nazari <amirmohammad.
Jun 3
Tynan McAuley
, …
Sriram R
17
May 23
TileLink questions and NVDLA performance
I have doubt on the integration of the dbb interface , how the 512-bit data is handled from the dbb
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TileLink questions and NVDLA performance
I have doubt on the integration of the dbb interface , how the 512-bit data is handled from the dbb
May 23