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hakam atassi
,
Jerry Zhao
3
Jul 25
TL interconnect under chisel 6.0
Hey Jerry, Thanks for the response. I spent a bit of time going over the chipyard repo since your
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TL interconnect under chisel 6.0
Hey Jerry, Thanks for the response. I spent a bit of time going over the chipyard repo since your
Jul 25
Raffaele Meloni
,
Jerry Zhao
7
Jul 23
Using development versions of Chisel and CIRCT
I am less familiar with how publish/versioning of the chisel-plugin works. Perhaps the `
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Using development versions of Chisel and CIRCT
I am less familiar with how publish/versioning of the chisel-plugin works. Perhaps the `
Jul 23
Nathan Kaplan
, …
Albert Ou
3
Jul 20
[Gemmini] flush command purpose
On Sat, Jul 20, 2024 at 12:35 PM 'Hasan Genc' via Chipyard <chip...@googlegroups.com>
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[Gemmini] flush command purpose
On Sat, Jul 20, 2024 at 12:35 PM 'Hasan Genc' via Chipyard <chip...@googlegroups.com>
Jul 20
Jongsang Yoo
, …
Jerry Zhao
8
Jul 19
Is there any RISC-V Processor with Vector Extension?
The vector unit for Rocket and Shuttle will be released soon, with chipyard integration. -Jerry On
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Is there any RISC-V Processor with Vector Extension?
The vector unit for Rocket and Shuttle will be released soon, with chipyard integration. -Jerry On
Jul 19
Yuan Dai
,
Jerry Zhao
3
Jul 18
The Usage of Custom_boot Pin
Hi Jerry, Thanks for your reply, which is helpful. I will learn more about the source code of it.
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The Usage of Custom_boot Pin
Hi Jerry, Thanks for your reply, which is helpful. I will learn more about the source code of it.
Jul 18
Jerry Ho
,
Jerry Zhao
3
Jul 16
Some confusion on tapout a chipyard based design
I just replied but it disappeared, so I replied here again. Thanks for your reply, and sorry for my
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Some confusion on tapout a chipyard based design
I just replied but it disappeared, so I replied here again. Thanks for your reply, and sorry for my
Jul 16
Vincent Ulitzsch
Jul 14
Chipyard Makefile -- Enable custom passes for CIRT/FIRRTL?
Let's say I compile the BOOM Core with the makefile provided by Chipyard: cd sims/verilator make
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Chipyard Makefile -- Enable custom passes for CIRT/FIRRTL?
Let's say I compile the BOOM Core with the makefile provided by Chipyard: cd sims/verilator make
Jul 14
Tim Heaton
,
Jerry Zhao
2
Jul 9
Connecting Multiple Chips created from WithHomogeneousMultiChip to a Single Blackbox
I think this doesn't quite exist yet... and it would be difficult to generalize. You can create a
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Connecting Multiple Chips created from WithHomogeneousMultiChip to a Single Blackbox
I think this doesn't quite exist yet... and it would be difficult to generalize. You can create a
Jul 9
Johnson Umeike
Jul 3
How to connect a RoCC Accelerator Module to the System Bus without talking to the Cache
Hi, I am quite new to Chipyard. I have a hardware message queue module implemented as a tightly-
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How to connect a RoCC Accelerator Module to the System Bus without talking to the Cache
Hi, I am quite new to Chipyard. I have a hardware message queue module implemented as a tightly-
Jul 3
陳冠穎
Jul 2
Is there any possibility to run generated SoC on Xilinx Alveo U50 or U55c?
Hi, I am quite new to Chipyard and Firesim. I found out that by using Firesim we got support for
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Is there any possibility to run generated SoC on Xilinx Alveo U50 or U55c?
Hi, I am quite new to Chipyard and Firesim. I found out that by using Firesim we got support for
Jul 2
Yuan Dai
,
Jerry Zhao
6
Jun 27
Rocket SoC Boot Process
Hi Jerry, Thanks for your response. My questions are solved, and I will learn more about this.
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Rocket SoC Boot Process
Hi Jerry, Thanks for your response. My questions are solved, and I will learn more about this.
Jun 27
TOBIAS KIM
, …
连浩丞
4
Jun 21
Connecting axi4_mem_0_clock to Vivado AXI4 controller
Are you generating the bitstream through the FPGA script in chipyard? I'm also in the process of
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Connecting axi4_mem_0_clock to Vivado AXI4 controller
Are you generating the bitstream through the FPGA script in chipyard? I'm also in the process of
Jun 21
Berke Bütün
Jun 20
Missing dtb File
I'm trying to install Chipyard 1.9.1 with firesim as my Hardware Simulator. I have followed the
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Missing dtb File
I'm trying to install Chipyard 1.9.1 with firesim as my Hardware Simulator. I have followed the
Jun 20
이하나
, …
Xiao Peng
4
Jun 16
Hwacha Segmentation Fault
Hi,I Got the same problem when I Simulate The Default Example. Have you solved this problem yet? 在
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Hwacha Segmentation Fault
Hi,I Got the same problem when I Simulate The Default Example. Have you solved this problem yet? 在
Jun 16
Yinuo Wang
Jun 14
Sky-130 commercial tutorial Place & Route fail
Hi all, I'm following the Sky130 commercial tutorial and I'm using Genus and Innovus. The
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Sky-130 commercial tutorial Place & Route fail
Hi all, I'm following the Sky130 commercial tutorial and I'm using Genus and Innovus. The
Jun 14
Aditya Badole
,
Jerry Zhao
4
Jun 13
Making changes to the device tree
IMO it is easier to hack around in SW to achieve this goal, than to mess around with the in-ROM-DTB.
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Making changes to the device tree
IMO it is easier to hack around in SW to achieve this goal, than to mess around with the in-ROM-DTB.
Jun 13
chihyu
Jun 13
Synthesis with Sky-130+OpenRoad for TinyRocket and GemminiSoCConfig
Hi, all I'm trying to synthesis the TinyRocket SoC using sky-130+openroad. In the ChipTop.
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Synthesis with Sky-130+OpenRoad for TinyRocket and GemminiSoCConfig
Hi, all I'm trying to synthesis the TinyRocket SoC using sky-130+openroad. In the ChipTop.
Jun 13
Jerry Zhao
,
Yuan Dai
2
Jun 12
Re: [chipyard] Rocket SoC Chip Boot Process
Hi Jerry, Thanks for your response and guidance! Best, Yuan 在2024年6月12日星期三 UTC+8 00:52:31<jerr...@
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Re: [chipyard] Rocket SoC Chip Boot Process
Hi Jerry, Thanks for your response and guidance! Best, Yuan 在2024年6月12日星期三 UTC+8 00:52:31<jerr...@
Jun 12
Patrick Schmidt
,
Jerry Zhao
7
Jun 11
Transmitting an executable binary to FPGA via Serial port
Thanks again, I will check it out! I have found the code for the UART TSI and wanted to know if there
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Transmitting an executable binary to FPGA via Serial port
Thanks again, I will check it out! I have found the code for the UART TSI and wanted to know if there
Jun 11
Arun Ravindran
,
David Byrd
4
Jun 10
Hammer fails on PAR while trying with vlsi turorial
I ran into the same problem. Were you able to find a workaround? On Thursday, May 23, 2024 at 12:41:
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Hammer fails on PAR while trying with vlsi turorial
I ran into the same problem. Were you able to find a workaround? On Thursday, May 23, 2024 at 12:41:
Jun 10
Zixian Cai
,
Jerry Zhao
4
Jun 6
regmapper.RegisterRouter vs tilelink.RegisterRouter
The latest version of the GCD example uses TLRegisterNode. -Jerry On Wed, Jun 5, 2024 at 9:39 PM
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regmapper.RegisterRouter vs tilelink.RegisterRouter
The latest version of the GCD example uses TLRegisterNode. -Jerry On Wed, Jun 5, 2024 at 9:39 PM
Jun 6
Jerry Ho
,
Jerry Zhao
2
Jun 5
How to run chipyard's unittest simulation in verilator?
That should work... you can also try `run-binary BINARY=none`, which should definitely work. -JErry
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How to run chipyard's unittest simulation in verilator?
That should work... you can also try `run-binary BINARY=none`, which should definitely work. -JErry
Jun 5
Tim Heaton
,
Jerry Zhao
3
Jun 4
Starting up a Chip using another Chip
Yup, this makes a lot of sense. I can see what you are referring to throughout the Chisel. As for the
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Starting up a Chip using another Chip
Yup, this makes a lot of sense. I can see what you are referring to throughout the Chisel. As for the
Jun 4
Brendon Chetwynd
, …
Hasan Genc
3
Jun 4
Optional Module I/O
Your issue is that the example code you gave won't even compile (let alone elaborate), right? If
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Optional Module I/O
Your issue is that the example code you gave won't even compile (let alone elaborate), right? If
Jun 4
Kathleen Feng
,
Jerry Zhao
3
May 31
I/O Pad Clock Domain
Hi Jerry, Great, thank you for the response and the pointers to existing configs! Kathleen On 5/30/24
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I/O Pad Clock Domain
Hi Jerry, Great, thank you for the response and the pointers to existing configs! Kathleen On 5/30/24
May 31
KAVSGAME
, …
202130...@whu.edu.cn
6
May 31
Plugin "clint" already registered
Thank you very much! I installed the latest tag chipyard v1.11.0 and gemmini v0.7.2 as your
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Plugin "clint" already registered
Thank you very much! I installed the latest tag chipyard v1.11.0 and gemmini v0.7.2 as your
May 31
Brendon Chetwynd
,
Jerry Zhao
5
May 30
Overriding verilog module name, not the instantiation
I'm not aware of one. An API for naming ClockSinkDomains has been added to rocket-chip. -Jerry On
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Overriding verilog module name, not the instantiation
I'm not aware of one. An API for naming ClockSinkDomains has been added to rocket-chip. -Jerry On
May 30
Hyunseo
,
Jerry Zhao
2
May 29
Inquiry About Hwacha CI Flow in Chipyard
Hwacha is not compatible with modern RISC-V toolchains. Hwacha additionally will be deprecated and
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Inquiry About Hwacha CI Flow in Chipyard
Hwacha is not compatible with modern RISC-V toolchains. Hwacha additionally will be deprecated and
May 29
Dieter
,
Jerry Zhao
2
May 28
RocketChip: Get rid of FixedClockBroadcast module
I thought an example showing this was done already, but the PR was never merged. I've updated the
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RocketChip: Get rid of FixedClockBroadcast module
I thought an example showing this was done already, but the PR was never merged. I've updated the
May 28
Chin Tsai
,
Jerry Zhao
2
May 28
Generate VCD file with difference name
No. This is not supported from the `make run-binary` targets. You can do some shell scripting to
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Generate VCD file with difference name
No. This is not supported from the `make run-binary` targets. You can do some shell scripting to
May 28