Chipyard

Hi i also have same problem did you solve it? 2023년 5월 26일 금요일 오후 1시 45분 5초 UTC+9에 xijin...@alumni.

I am not sure what you are asking for. The Rocket core executes RISC-V binaries, and can be simulated

I found out the problem. The clock name should be "clock_uncore" instead of "

Hello all, I have a question while running rocket soc on VCU118 by following the chipyard doc. In the

Gentle reminder. On Monday, April 8, 2024 at 5:36:49 PM UTC+9 Sameer Deshmukh wrote: On a closer look

I'm new to chipyard, but quite familiar with Linux. I followed the chipyard.readthedocs.io with v

Hello, I am encountering this error while trying to generate an SoC with some custom blocks: Caused

Hello, I'm a newbie in FPGA development and I'm now trying to deploy a modified rocket-chip

The documentation at https://docs.fires.im/en/stable/Getting-Started-Guides/On-Premises-FPGA-Getting-

I am trying to integrate my custom processor into chipyard flow. I have few signals which I would

Hi, I am using TL2AXI4 to bridge a tilelink-interface module to AXI bus. In the spec SiFive TileLink

Hi Jerry, Thanks for the response. I found https://github.com/sifive/plic-baremetal to be helpful in

additional info: the first result is when the binary does not exist, second one is when the binary

That sounds odd to me, but it wouldn't be totally surprising. You can use the chisel dontTouch

You can patch it.. Personally, I recommend switching to the latest version of chipyard and firesim on

Hello Kin, You should take a look in the chipyard/tests directory. There are some examples on how to

Can you try running the latest main branch? I think we caught this and fixed it, but haven't

We are working on developing a custom MMIO peripheral and need to have a signal to connect to the

Hi all, I'm diving into RTL simulation of multicore cache coherency in Chipyard and need your

I found that online version of yEd does not render the graph as the graphml is described but the

Hi all, i have the same problem when i am trying to login with the 'fpga' password. I am

https://github.com/firesim/firesim/issues/1692 Gon Solo schrieb am Samstag, 16. März 2024 um 18:09:32

Hi All, I have been working on building a TCAM module in chipyard and I am facing an odd problem. As

Hello! Chipyard commit hash: b592934 Just making it clear that I'm new to the chipyard. I am able

Hi all, I am trying to generate RTL code of rocket-chip via chipyard. All I need is a RTL code of

Update: I was able to get it working by building the AGFI from scratch on Chipyard 1.11.0 On Thursday

Hi all, I implemented a custom CSR in tile/CustomCSRs.scala. I am able to get signals from the CSR by

I'm trying to get a functioning bitstream of a Boom core implementation over the arty100T board

Compile your code with the linker file and generate the elf for your baremetal program. Then you can

Re: Faild to build workload br-base.json On Monday, February 26, 2024 at 8:11:36 AM UTC+8 黃浩展 wrote: