Groups

Chipyard

Contact owners and managers

1–30 of 973

This google group is the best place to ask questions about Chipyard. Learn more at https://github.com/ucb-bar/chipyard

0 selected

Jan 1

Is there any LLM/SLLM demo running with gemmini and RVV?

Hi, Just as mentioned , Is there any LLM/SLLM demo running with gemmini and RVV? I think this is an

unread,

Is there any LLM/SLLM demo running with gemmini and RVV?

Hi, Just as mentioned , Is there any LLM/SLLM demo running with gemmini and RVV? I think this is an

Jan 1

Musa Kartal Engin

12/24/25

Issues running UART TSI on Nexys Video with GemminiNoDDR15MHzNexysVideoConfig - Stuck at "Wrote 0"

Soru İçeriği (Body): Hi everyone, I'm trying to bring up Gemmini on a Nexys Video board using the

unread,

Issues running UART TSI on Nexys Video with GemminiNoDDR15MHzNexysVideoConfig - Stuck at "Wrote 0"

Soru İçeriği (Body): Hi everyone, I'm trying to bring up Gemmini on a Nexys Video board using the

12/24/25

Tatsuya, … Ashbin Shiju10

12/18/25

How to Implement Custom IP Core?

To add Custom Core into Chipyard : in the chipyard/generators/mytile/src/main/resources/vsrc add the

unread,

How to Implement Custom IP Core?

To add Custom Core into Chipyard : in the chipyard/generators/mytile/src/main/resources/vsrc add the

12/18/25

Jongsang Yoo, … Fizza Haq4

12/17/25

[Spike-as-a-tile] Verliator RTL simulation error with custom ISA

Hello, I am hitting the same TileLink assertion reported in this thread. I would like to emphasize

unread,

[Spike-as-a-tile] Verliator RTL simulation error with custom ISA

Hello, I am hitting the same TileLink assertion reported in this thread. I would like to emphasize

12/17/25

Maria Jose Belda Beneyto, … Tianhao Cai7

12/8/25

Gemmini design doesn't fit on instance target

Dear MªJosé, Thinh, From my previous experience, FP units are very LUTs-costly. You can try to use

unread,

Gemmini design doesn't fit on instance target

Dear MªJosé, Thinh, From my previous experience, FP units are very LUTs-costly. You can try to use

12/8/25

Eduardo Schwarz Danni

12/6/25

Geting stuck in verilog generation from firrtl

Hi, I am trying to generate the verilog (and later run simulations) from my design, but I get stuck

unread,

Geting stuck in verilog generation from firrtl

Hi, I am trying to generate the verilog (and later run simulations) from my design, but I get stuck

12/6/25

Eduardo Schwarz Danni

12/6/25

Problems with verilog generation

Hi, I've created a design that is a modification of the BOOM, and when trying to generate the

unread,

Problems with verilog generation

Hi, I've created a design that is a modification of the BOOM, and when trying to generate the

12/6/25

12/1/25

Issue setting up riscv-tools

Hi, I get the following error when I try to set up Chipyard on my local machine with riscv-tools:

unread,

Issue setting up riscv-tools

Hi, I get the following error when I try to set up Chipyard on my local machine with riscv-tools:

12/1/25

陳冠穎, … Ranjith Kumar5

12/1/25

Is there any possibility to run generated SoC on Xilinx Alveo U50 or U55c?

Hi, Can you brief the method you have followed to successfully program the zcu102 using chipyard

unread,

Is there any possibility to run generated SoC on Xilinx Alveo U50 or U55c?

Hi, Can you brief the method you have followed to successfully program the zcu102 using chipyard

12/1/25

11/20/25

Saturn VPU cycle counter

Hello I'm trying to check the cycle count in Saturn VPU(+Rocket core) using Verilator. My

unread,

Saturn VPU cycle counter

Hello I'm trying to check the cycle count in Saturn VPU(+Rocket core) using Verilator. My

11/20/25

11/18/25

Understanding Gemmini’s Uncached TileLink Path and L1/L2 Coherence Implications

Hi everyone, I'm trying to better understand how TileLink behaves in Chipyard specifically when

unread,

Understanding Gemmini’s Uncached TileLink Path and L1/L2 Coherence Implications

Hi everyone, I'm trying to better understand how TileLink behaves in Chipyard specifically when

11/18/25

11/17/25

Chipyard with Xilinx KC705 board

Dear all, I am new to Chipyard and my group wants to implement Rocket and BOOM cores on KC705 because

unread,

Chipyard with Xilinx KC705 board

Dear all, I am new to Chipyard and my group wants to implement Rocket and BOOM cores on KC705 because

11/17/25

11/10/25

How can I invoke a RoCC accelerator to execute a program on a FireMarshal system?

In the following configuration (where an additional Tweaks has been added to the FPGA), programs

unread,

How can I invoke a RoCC accelerator to execute a program on a FireMarshal system?

In the following configuration (where an additional Tweaks has been added to the FPGA), programs

11/10/25

11/10/25

how can i use rocc accelerator run accum.riscv and charcount.riscv on firemarshal linux

I modified vcu118 to deploy on zcu102, and successfully ran firemarshal linux on it. I wrote a "

unread,

how can i use rocc accelerator run accum.riscv and charcount.riscv on firemarshal linux

I modified vcu118 to deploy on zcu102, and successfully ran firemarshal linux on it. I wrote a "

11/10/25

10/18/25

Xcelium reported multiple "Unknown option *** "

I'm using hammer under directory "chipyard/vlsi". The OS is CentOS 7.9. Xcelium version

unread,

Xcelium reported multiple "Unknown option *** "

I'm using hammer under directory "chipyard/vlsi". The OS is CentOS 7.9. Xcelium version

10/18/25

shravan ramesh, Junaid amjad2

9/30/25

issue on scripts

This is definitely some env issue. Seems like you are using some older version of chipyard, switch to

unread,

issue on scripts

This is definitely some env issue. Seems like you are using some older version of chipyard, switch to

9/30/25

이신우 / 학생 / 전기·정보공학부, Matthew Edwin Weingarten2

9/30/25

Generating firrtl IR with Top circuit as RocketTile

Hi, Can you give more insight into what you will do with the generated firrtl IR? Are you using CIRCT

unread,

Generating firrtl IR with Top circuit as RocketTile

Hi, Can you give more insight into what you will do with the generated firrtl IR? Are you using CIRCT

9/30/25

Jerry Ho, … Scott Eckart6

9/23/25

Best Practice of witing bootrom for chipyard based ASIC design

Hi Jerry, Not sure if you'll see this (being that this thread is now a year old) - but any help

unread,

Best Practice of witing bootrom for chipyard based ASIC design

Hi Jerry, Not sure if you'll see this (being that this thread is now a year old) - but any help

9/23/25

thh, Học Nguyễn Hữu2

9/23/25

Generate bitstream for only NoC-Standalone config

Hi there, I'm fourth grade of UIT-HCM, I have the same project topic as your (maybe). If you are

unread,

Generate bitstream for only NoC-Standalone config

Hi there, I'm fourth grade of UIT-HCM, I have the same project topic as your (maybe). If you are

9/23/25

이신우 / 학생 / 전기·정보공학부

9/23/25

Generating RocketTIle firrtl IR

Hello, I am an undergraduate student studying RocketChip Generator. I am having a hard time

unread,

Generating RocketTIle firrtl IR

Hello, I am an undergraduate student studying RocketChip Generator. I am having a hard time

9/23/25

9/23/25

[Chipyard/Gemmini] Simulation Fails with "ReservationStation.scala" Assertion for Softmax/Layernorm Workloads

Hello Chipyard Developers and Community, I am encountering a simulation assertion failure when

unread,

[Chipyard/Gemmini] Simulation Fails with "ReservationStation.scala" Assertion for Softmax/Layernorm Workloads

Hello Chipyard Developers and Community, I am encountering a simulation assertion failure when

9/23/25

9/23/25

Using SRAM Compiler to stub in Verilog models for synthesis

Hello all Due to my current configuration my memory complier is on a different machine than chipyard

unread,

Using SRAM Compiler to stub in Verilog models for synthesis

Hello all Due to my current configuration my memory complier is on a different machine than chipyard

9/23/25

9/8/25

Marking DRAM Region uncacheable

Hello, I am looking to treat a region of DRAM as uncacheable. I am using the FASED model. I basically

unread,

Marking DRAM Region uncacheable

Hello, I am looking to treat a region of DRAM as uncacheable. I am using the FASED model. I basically

9/8/25

Lucas Arruk, Junaid amjad2

8/30/25

Issue on running CoreMark bare-metal on RocketCore

Hi, I ran the same test with the default rocket config and it's working fine. Well it did not

unread,

Issue on running CoreMark bare-metal on RocketCore

Hi, I ran the same test with the default rocket config and it's working fine. Well it did not

8/30/25

John Charlie, Junaid amjad2

8/30/25

Any Documentation about SoC registers in default Chipyard configurations?

Hi, There is not such a datasheet or something, but we do get .json files listing all memory mapped

unread,

Any Documentation about SoC registers in default Chipyard configurations?

Hi, There is not such a datasheet or something, but we do get .json files listing all memory mapped

8/30/25

8/29/25

SD card becomes slower after booting Firemarshal image

After booting buildroot successfully with an SD card speed of 25MHz, reading data from the second

unread,

SD card becomes slower after booting Firemarshal image

After booting buildroot successfully with an SD card speed of 25MHz, reading data from the second

8/29/25

Kelly Xu, Junaid amjad5

8/25/25

Swapping ROM and DRAM addresses - Sodor Core

Thank you, this worked! On Monday, August 25, 2025 at 12:17:45 PM UTC-4 junaida...@gmail.com wrote:

unread,

Swapping ROM and DRAM addresses - Sodor Core

Thank you, this worked! On Monday, August 25, 2025 at 12:17:45 PM UTC-4 junaida...@gmail.com wrote:

8/25/25

Nick Lee, … jinhui pan5

7/7/25

FPGA prototyping: cannot detect sd card 2nd partition

I have same problem also. Please contact me if someone have solved this problem. I add CONFIG_MMC=y,

unread,

FPGA prototyping: cannot detect sd card 2nd partition

I have same problem also. Please contact me if someone have solved this problem. I add CONFIG_MMC=y,

7/7/25

edward mulier, Tung Hoang2

7/1/25

Area of 16bit floating-point Gemmini

Table 3 of the below paper has MAC int8 and fp16 area https://arxiv.org/pdf/1811.01721 On Tue, Jul 1,

unread,

Area of 16bit floating-point Gemmini

Table 3 of the below paper has MAC int8 and fp16 area https://arxiv.org/pdf/1811.01721 On Tue, Jul 1,

7/1/25

7/1/25

How to enable more than foure RoCC accelerators within one core?

Dear authors, I am a beginner with Chipyard, and I am curious about the RoCC extension. Here are some

unread,

How to enable more than foure RoCC accelerators within one core?

Dear authors, I am a beginner with Chipyard, and I am curious about the RoCC extension. Here are some

7/1/25

Search

Clear search

Close search

Google apps

Main menu