Re: Electronic Devices And Circuits By Jb Gupta Pdf Download
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K. Cho, X. Fong, S. K. Gupta, "Exchange-Coupling-Enabled Electrical-Isolation of Compute and Programming Paths in Valley-Spin Hall Effect based Spintronic Device for Neuromorphic Applications", Device Research Conference (DRC), 2021.
A. A. Saki, S. H. Lin, M. M. Alam, S. K. Thirumala, S. K. Gupta and S. Ghosh, "A Family of Compact Non-Volatile Flip-Flops with Ferroelectric FET", IEEE Transactions on Circuits and Systems I: Regular Papers, 2019.
N. Thakuria, A. K. Saha, S. K. Thirumala, B. Jung and S. K. Gupta, "Oscillators Utilizing Ferroelectric Based Transistors and their Coupled Dynamics", IEEE Transactions on Electronic Devices (TED), 2019.
Zhesheng Shen, Srivatsa Srinivasa, Ahmedullah Aziz, Suman Datta, Vijaykrishnan Narayanan, Sumeet Kumar Gupta, "SRAMs and DRAMs with separate Read-Write Ports Augmented by Phase Transition Materials", IEEE Transactions on Electronic Devices (TED), 2019.
S. K. Thirumala, S. Jain, A. Raghunathan and S.K. Gupta, "Non-Volatile Memory utilizing Reconfigurable Ferroelectric Transistors to enable Differential Read and Energy-Efficient In-Memory Computation", Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2019.
S. Dutta, A. K. Saha, P. Panda, W. Chakraborty, J. Gomez, A. Khanna, S. Gupta, K. Roy, S. Datta, "Biologically Plausible Ferroelectric Quasi-Leaky Integrate and Fire Neuron", Symposium on VLSI Technology, 2019.
Yuhua Liang, Xueqing Li, Sumitha George, Srivatsa Srinivasa, Zhangming Zhu, Sumeet Kumar Gupta, Suman Datta, Vijaykrishnan Narayanan, "Influence of Body Effect on Sample and Hold Circuit Design using Negative Capacitance FET", IEEE Transactions on Electronic Devices (TED), 2018.
S. Srinivasa, X. Li, M. Chang, J. Sampson, S. K. Gupta and V. Narayanan, "Compact 3-D-SRAM Memory With Concurrent Row and Column Data Access Capability Using Sequential Monolithic 3-D Integration", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018.
S. Srinivasa, A. K. Ramanathan, X. Li, W. Chen, F. Hsueh, C. Yang, C. Shen, J. Shieh, S. K. Gupta, M. M. Chang, S. Ghosh, J. Sampson and V. Narayanan, "A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support", Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2018.
S. K. Thirumala, A. Raha, H. Jayakumar, K. Ma, V. Narayanan, V. Raghunathan and S. K. Gupta "Dual Mode Ferroelectric Transistor based Non-Volatile Flip-Flops for Intermittently-Powered Systems", Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2018. (Best Paper Nominee)
A. De, A. Iyengar, M. N. I. Khan, S-H. Lin, S. Thirumala, S. Ghosh and S. K. Gupta, "CTCG: Charge-Trap Based Camouflaged Gates for Reverse Engineering Prevention", IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2018.
A. K. Saha, P. Sharma, I. Dabo, S. Datta and S. K. Gupta, "Ferroelectric transistor model based on self-consistent solution of 2D Poisson's, non-equilibrium Green's function and multi-domain Landau Khalatnikov equations", IEEE International Electron Devices Meeting (IEDM), 2017.
A. Aziz, N. Jao, S. Datta, V. Narayanan and S. K. Gupta, "A computationally efficient compact model for leakage in cross-point array", International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2017.
S. R. Srinivasa, K. Mohan, W. Chen, K. Hsu, X. Li, M. Chang, S. K. Gupta, J. Sampson and V. Narayanan, "Improving FPGA design with monolithic 3D integration using high dense inter-stack via", IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017.
P. Sharma, K. Tapily, A. K. Saha, J. Zhang, A. Shaughnessy, A. Aziz, G. L. Snider, S. K. Gupta, R. D. Clark and S Datta, "Impact of total and partial dipole switching on the switching slope of gate-last negative capacitance FETs with ferroelectric hafnium zirconium oxide gate stack", Symposium on VLSI Technology, 2017.
S. Srinivasa, A. Aziz, N. Shukla, X. Li, J. Sampson, S. Datta, J. P. Kulkarni, V. Narayanan and S. K. Gupta, "Correlated material enhanced SRAMs with robust low power operation", IEEE Transactions on Electron Devices (TED), 2016.
M. S. Kim, W. C. Wissing, X. Li, J. Sampson, S. Datta, S. K. Gupta and V. Narayanan, "Comparative area and parasitics analysis in FinFET and heterojunction vertical TFET standard cells", ACM Journal on Emerging Technologies in Computing Systems (JETC), 2016.
X. Yin, A. Aziz, J. Nahas, S. Datta, S. K. Gupta, M. Niemier and X. S. Hu, "Exploiting ferroelectric FETs for low-power non-volatile logic-in-memory circuits", Proceedings of the 35th International Conference on Computer-Aided Design, 2016.
D. Wang, S. George, A. Aziz, S. Datta, V. Narayanan and S. K. Gupta, "Ferroelectric transistor based non-volatile flip-flop", Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2016.
S. George, A. Aziz, X. Li, M. S. Kim, S. Datta, J. Sampson, S. K. Gupta, V. Narayanan, "Device circuit co design of FEFET based logic for low voltage processors", IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016.
S. George, K. Ma, A. Aziz, X. Li, A. Khan, S. Salahuddin, M. Chang, S. Datta, J. Sampson, S. K. Gupta and V. Narayanan, "Nonvolatile memory design based on ferroelectric FETs", Proceedings of the 53rd Annual Design Automation Conference, 2016.
S. K. Gupta, A. Aziz, N. Shukla and S. Datta, "On the potential of correlated materials in the design of spin-based cross-point memories", IEEE International Symposium on Circuits and Systems (ISCAS), 2016.
N. Shukla, A. V. Thathachary, A. Agrawal, H. Paik, A. Aziz, D. G. Schlom, S. K. Gupta, R. E. Herbert and S. Datta "A steep-slope transistor based on abrupt electronic phase transition", Nature communications, 2015
A. Aziz, N. Shukla, S. Datta and S. K. Gupta, "Implication of hysteretic selector device on the biasing scheme of a cross-point memory array", International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2015.
A. Aziz, N. Shukla, S. Datta and S. K. Gupta, "COAST: Correlated material assisted STT MRAMs for optimized read operation", Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2015.
A. Aziz, W. C. Wissing, M. S. Kim, S. Datta, V. Narayanan and S. K. Gupta, "Single-ended and differential MRAMs based on spin Hall effect: A layout-aware design perspective", IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2015.
K. Ma, N. Chandramoorthy, X. Li, S. K. Gupta, J. Sampson, Y. Xie and V. Narayanan, "Using Multiple-Input NEMS for Parallel A/D Conversion and Image Processing", IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2015.
M. S. Kim, W. C. Wissing, J. Sampson, S. Datta, V. Narayanan and S. K. Gupta, "Comparing energy, area, delay tradeoffs in going vertical with CMOS and asymmetric HTFETs", IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2015.
A. Aziz, N. Shukla, S. Datta and S. K. Gupta, "Read optimized MRAM with separate read-write paths based on concerted operation of magnetic tunnel junction with correlated material", 73rd Annual Device Research Conference (DRC), 2015.
S. K. Gupta, G. Panagopoulos and K. Roy, NBTI in n-type SOI access FinFETs in 6T SRAM and its impact on cell stability and performance", IEEE Transactions on Electron Devices, vol. 59, no. 10, Oct. 2012.
M. Sharad, S. K. Gupta, S. Raghunathan, P. Irazoqui and K. Roy, " Low-Power Architecture for Epileptic Seizure Detection Based on Reduced Complexity DWT", ACM Journal on Emerging Technologies in Computing Systems, vol. 8, no. 2, June 2012.
N. N. Mojumder, S. K. Gupta, S. H. Choday, D. E. Nikonov and K. Roy, Three Terminal Dual-Pillar STT-MRAM Device for High-Performance Robust Memory Applications," IEEE Transactions on Electron Devices, vol. 58, no. 5, May 2011.
M. J. Kumar, V. Venkataraman and S. K. Gupta, "A New Grounded Lamination Gate (GLG) for Diminished Fringe Capacitance Effects in High-K Gate Dielectric MOSFETs", IEEE Transactions on Electron Devices, vol. 53, no. 10, October 2006.
A. Goud, S. K. Gupta, S. H. Choday and K. Roy, Atomistic Tight-Binding based Evaluation of Impact of Gate Underlap on Source to Drain Tunneling in 5 nm Gate Length Si FinFETs, Device Research Conference (DRC), 2013.
M. J. Kumar, V. Venkataraman and S. K. Gupta, "A New Grounded Lamination Gate (GLG) SOI MOSFET for Diminished Fringe Capacitance Effects," Technical Proceedings of the 2006 NSTI Nanotechnology Conference and Trade Show, pp. 709-712, 2006.
M. J. Kumar, V. Venkataraman and S. K. Gupta, "Compact Modeling of Parasitic Internal Fringe Capacitance and its effect on the Threshold Voltage of High-K Gate Dielectric SOI MOSFETs", Int. Workshop on the Physics of Semiconductor Devices, 2005.
Electronic devices and circuits by sanjeev gupta PDF ??? ??? Download Zip dimensional heterostructure nanowires (NWs) have attracted a large attention due to the possibility of easily tuning their energy gap, a useful property for application to next generation electronic devices. In this work, we propose new core/shell NW systems where Ge and Si shells are built around very thin As and Sb cores. The modification in the electronic properties arises due to the induced compressive strain experienced by the metal core region which is attributed to the lattice-mismatch with the shell region. As/Ge and As/Si nanowires undergo a semiconducting-to-metal transition on increasing the diameter of the shell. The current-voltage (I-V) characteristics of the nanowires show a negative differential conductance (NDC) effect for small diameters that could lead to their application in atomic scale device(s) for fast switching. In addition, an ohmic behavior and upto 300% increment of the current value is achieved on just doubling the shell region. The resistivity of nanowires decreases with the increase in diameter. These characteristics make these NWs suitable candidates for application as electron connectors in nanoelectronic devices.Since the synthesis of carbon nanotubes (CNTs) in the beginning of 1990s1, one dimensional (1D) nanostructures have attracted a huge interest in the last three decades. CNTs were believed to be among the most important building blocks for the next generation electronic devices. After decades of progress in nanotechnology, both theoretically and experimentally, nanowires have opened up substantial opportunities for the development of nanoelectronic and optoelectronic devices. Therefore, several studies have demonstrated the application of nanowires (NWs) in the field of electron devices2,3,4,5,6,7,8,9, logic gates2,10,11, optoelectronics12,13,14, photonics15,16, chemical and biological sensing devices10,17,18,19,20, non-volatile memories21 etc. Likewise, 1D heterostructure NWs have been extensively studied for next-generation device applications22,23.Recently, extensive efforts have been devoted to grow and study core/shell NWs consisting of semiconductor/semiconductor24,25, semiconductor/metal26, metal/metal oxide27,28, metal oxide/metal oxide29,30,31,32, metal/metal33,34 heterostructure(s). Particularly, semiconductor core/shell NWs such as SiGe, have gained much attention due to their remarkable transport and optical properties22 which are attributed to the spatial localization of electrons and holes. The electronic properties of these NWs have a strong dependence on their size, shape and chemical composition35. For example, Amato et al. have shown that the geometry and composition of Si/Ge core/shell NWs strongly influence their thermodynamic stability and electronic properties. Peng et al.36 have shown that the intrinsic strain between Ge and Si layers is responsible for the reduction of the band gap in Si/Ge core/shell NWs from their pristine counterparts. In addition, external strain can be used to tune the band gap of the NWs, and promote a direct-to-indirect (or vice-versa) band gap transition. It has also been reported that Si/Ge NW quantum dot FET shows a superior performance over the Si nanowire FET due to a gate field induced switching mechanism37. Recently, synthesized Si/SiC core/shell NWs paved the way to biocompatible nanowire based sensors due to the chemically inertness and hydrophilic surface of SiC38. This semiconducting core/shell NWs have obtained enormous applications in the field of FET, IC circuits, logic gates, solar cells in nanoelectronic devices22,37,39,40. The versatile electronic, transport and optical properties of core/shell NWs which depend on the configuration and composition of the core and shell of the NWs have motivated us to go beyond IV-IV and III-V nanowire systems and study the electronic and trans
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