Recent functional architecture projects

[Rob Stewart]

Hi folks,

We're encouraged to come across multiple active/recent functional hardware architecture research projects.

Below are the projects we are aware of, please feel free to add those we've missed.

Cephalopode (University of Chalmers) - Part of the Octopi project. A custom processor aimed at functional language execution for IoT devices (MEMOCODE 2020). See Jeremy Pope's recent PhD thesis. Also the PHOENIX project, a general-purpose multi-core processor with memory storage and efficient computational logic units interconnected with a mesh network-on-chip (MEMSYS 2017).

Cecil Accetti (PhD student, Shanghai Jiao Tong University) - Invented structured combinators, a hardware-friendly generalised representation of combinators (IEEE Computer Architecture Letters 2022).

HAFLANG project (Heriot-Watt University) - Developing Heron with Clash, a template-instantiation based processor (IFL 2023) and a concurrent garbage collector (Haskell 2024). We are also developing a processor with Chisel, to execute structured combinators. Our website.

PilGRIM (University of Twente) - A pipelined ISA-based processor specialised for the G-machine execution model for compiled graph reduction (IFL 2010).

Massimult (German based startup) - A machine language LambdaM for an abstract machine Matrima, based on combinators. A recent draft paper shared by Jurgen Nicklisch-Franken and their website.

Reduceron (University of York) - a graph reduction architecture that implements template instantiation. The work strongly influenced our Heron architecture. Their JFP 2012 paper and their website.

Zarf (University of California) - A verifiable processor with a purely functional instruction set. Their website.

What other functional architecture projects are people aware of?

Best wishes,

Rob

[Cecil Accetti]

Hello everyone,

I'm glad to join this mailing list. Thanks @Rob Stewart for the invitation!

I'd like to add a shameless plug here, as the path to the fun instruction-set architecture, as presented in the 2022 CAL paper, also included many iterations of the design of the instruction set and the microarchitectures that implemented it.

ISCAS 2020:  'Blackbird CPU' https://doi.org/10.1109/ISCAS45731.2020.9180772

VLSI-SoC 2022: An overview of the fun project. During this time many others microarchitectures have been developed internally, from small stack machines (kiskadee) to hybrid functional-imperative (Caracara) pipelines.

https://doi.org/10.1109/VLSI-SoC54400.2022.9939644

There was also work on exploring the design of a purely-functional realtime kernel, called funk, presented as a MSc thesis at SJTU.

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The website of the fun ISA, http://wiki.fun-arch.org/, has not been updated in a while (my fault), but the plan is to return to it, starting with a new version of the draft of the ISA specification, in the coming weeks (tentative before Christmas).

The main goal of the fun ISA is to be an open-source specification architecture, so any feedback is welcome, and suggestions that improve the architecture are more than welcome.

I truly believe that standardizing the architecture layer in the most efficient form (whatever that is) is an essential step on the way to practical (and useful) functional processors. The RISC-V project is proof that the right ecosystem - standard toolchains, tests and benchmarks, a reference implementation, and a community-driven specification - is capable to set itself as a commercially-viable option among other architectures. User base increases when people can share their software, and they can only do it when the architecture standard is stable.

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All the best, and lets keep up the good work!

Cecil

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