Paragonx Tool
Beatrix Gerke
If I have a RCE .spf file for a top level cell (for example Cell A) which is comprised of multiple sub-blocks, can I use this same RCE file on simulations where I am only using sub blocks in a test bench?
To clarify in an example:
Assume the top level cell (Cell A) is comprised of sub-blocks X, Y, and Z, and I only have the parasitic extraction of Cell A (top level). Now let's say I have a new test bench that is only simulating sub-block Y and miscellaneous logic. Can I include this SAME RCE of the top-level Cell A in the .spf files and if so, will Cadence be able to pull the appropriate parasitic data on the nets that I have for sub-block Y?
It rather depends on whether the DSPF is hierarchical. If it's flat, then no (for fairly obvious reasons). If it's hierarchical and the sub-blocks exist as separate .SUBCKT entries (DSPF is SPICE-like), then it should work, I think; Spectre should tell you if it has a problem finding a match or not.
What might be the reason, to use higher-hierarchy level parasitic extraction to simulate lower-level block?
Is it required to take into account accurate parasitics (affected by high hierarchy layout), or unavailability (or difficulty to extract) lower-level block?
1. If the lower level block has connections that extend from it which are deemed "critical", then if the higher level block's parasitic routing elements are not included, one cannot establish the signal integrity of those "critical" nets of the lower level block.
2. Secondly, the next level of hierarchy (or higher) may have other traces that cross traces of the lower level block. Hence, the use of the higher level of extraction allows one to assess any potential crosstalk into or out of the subcircuit traces in the lower level block.
3. Thirdly, the higher level extraction may contain power or ground traces that form "power grids" that connect to the lower-level block. Hence, without the higher level extracted view based netlist, the actual power or ground resistances of the lower level block cannot be accurately simulated with only an extracted view of the lower level block. This view will also be required in any type of electromigration audit to assess trace current densities are less than the values required for one's reliability requirement.
Does this help your understanding? Of course, from a simulation time perspective, using the an extracted view based netlist for the lowest possible level of schematic hierarchy is preferred - but there are times when the use of a higher schematic hierarchy based extracted view is necessary.
Thank you - yes, this makes a perfect sense to me.
Basically, all three reasons you presented, are related to "interaction" between lower-hierarchy level blocks with each other and with higher hierarchy elements, which makes block-level simulation and verification inaccurate (sometimes - very inaccurate, leading to a complete design failure).
We see this sort of effects (caused by parasitics - you do not see this interaction at the schematic level) all the time, when doing analysis at the top level.
The problem is (especially in advanced nodes, lime 7nm or 5nm) - the size and complexity of the top hierarchy level is so high, that standard tools (SPICE, IR/EM, etc.) take too long to be practical.
So, new approaches and solutions are required - and there are a lot of opportunities for innovation in this area.
That's precisely why there has been innovation in this area. Spectre X technology involves mechanisms to do advanced parasitic reduction - whilst there are a lot of parasitics in advanced nodes, the network can certainly be reduced considerably without a significant impact on accuracy, plus it has mechanisms for more efficient simulation and better scalability across multiple cores and even distributed to multiple machines with a reduced memory footprint.
Another factor is - when electrical results from SPICE simulation look bad - where, which layout shape and parasitic elements are causing this?
I don't think that an RC reduction can help with this, for obvious reason - irrespective of the simulation speed.
You can do that part with sensitivity analysis - you can do some sensitivity analysis on the parasitics (although that will need more simulation to be run in order to capture the impact of variations in the parasitics to variations in the measurements). It's not that straightforward to directly infer the impact of an individual parasitic to the output measurements otherwise.
If I may add to Andrew's prior comments regarding spectre X...we have adopted its use recently and have found it does significant reduce simulation times for post-layout based netlist simulations. I, personally, have now done a number of comparisons of the results from a spectre X simulation with a spectre +aps simulation and found the two sets of data correlate well for circuits that require high levels of simulator accuracy.
Determining the root cause of trace parasitic based, or coupling based mechanism effects due to layout effects is not really the function of any simulator in my view. Maybe I do not fully understand your comment? One can certainly perform sensitivity analyses as Andrew suggests to better understand which parasitic elements contribute to your observed undesired behavior. However, our approach involves using the actual layout to determine trace parasitics along a specific set of traces (including parasitic elements due to its trace segments, vias, and neighboring elements) using an analysis tool we developed. This provides us with an excellent means of establishing which layout features are responsible for undesired circuit performance.
There is a tool called ParagonX by a company called Diakopto ( ) that claims to be able to perform such an analysis. I have never tried it, however, so I have no idea how well it works in practice. You can find some more details at -simulation-parasitics-do-we-need-more-speed-insight-ershov/ (also written by a guy called Maxim...).
Thank you! I was not aware of their ParagonX tool. We have a custom tool that we use for what I believe is a similar function. However, I contacted diakopto to find our some more information - thank you again!
ParagonX accelerates the analysis, debugging and optimization of integrated circuits (IC) design challenges caused by layout parasitics. By providing actionable insights to help engineers quickly and easily pinpoint bottlenecks and root causes, ParagonX helps Silicon Creations enhance the performance, power, robustness, and reliability of their suite of precision and general-purpose timing PLLs, oscillators, low-power, high-performance SerDes and high-speed differential I/Os.
Parasitics are unintended elements in IC designs that degrade circuit performance, precision, power efficiency, robustness, and reliability. The ever-increasing need for higher density, faster speed, and greater precision of integrated circuits, coupled with continued migration to more advanced technology nodes have redefined the role of parasitics in IC design. The power-performance-area (PPA) metric and time-to-market of modern ICs are now dominated by on-chip interconnects and layout parasitics. Debugging the root causes of IC design problems has become extraordinarily difficult, tedious, and time-consuming.
ParagonX features a robust set of tools for rapid electrical, capacitive, structural, connectivity and net-matching analysis and visualization. Information showing the most and least critical areas to be fixed are highlighted on the circuit layout, enabling designers to see where trade-offs can be made to optimize power, performance, and area. ParagonX helps reduce IC debugging and optimization time from days or weeks down to minutes or hours.
Dear all,
Here is chipR.
Which is based on Klayout, I use it to extract chip's metal parasitic Resistance.
Also, it can extract PCB's metal parasitic resistance.
Maybe it is useful for you.
Hi
By now, I have not any idea about a license. It seems that there are many types of licenses in the world.
I am confused by them. So I write the words "free for personal use at home" just because of the clear meaning.
"personal "-->not for business
"at home"--> not for company
I find there is very little free tool to do this. So I try to do a simple tool.
This "chipR" uses one simple and different algorithm to extract the parasitic parameters.
I compare this tool's result to other time-consuming EDA or finite element methods. It has a good match result.
It is fast, accurate, easy.
ChipR works great - thanks for posting.
One thing it doesn't appear to do is post process the results.
Is there a way to get voltage maps and current density maps from the results?
Thanks
that was some time ago ... anyway, what about this ChipR tool .. is it still around? Link doesn't seem to work.
Not sure if it is comparable, but there were also discussions about the integration of FastHenry into KLayout. Does anyone know if there is some progress in terms of R(C)-extraction (either as Klayout module or standalone).
BTW, OpenRCX seems to work with DEF files only, thus, it seems not usable in a general context.
I am looking for information about basic algorithms and approaches for implementing such a feature - if anyone comes across a description how the OpenRCX algorithm works, let me know. Honestly this code is not easy to read.
Diakopto announced today that eTopus, a pioneer of ultra-high speed ADC/DSP-based SerDes for wireline applications, has chosen the ParagonX platform and methodology for integrated circuits (IC) debugging and design improvement. ParagonX empowers eTopus engineers to quickly find the root causes of bottlenecks caused by layout parasitics, delivering actionable insights into how to fix and fully optimize their IC designs.
ParagonX offers a new methodology that delivers insights to assist design, layout and CAD engineers to quickly and easily pinpoint bottlenecks and the sources of IC design problems caused by parasitics. It is orders of magnitude faster than other EDA solutions, and helps engineers quickly find the few critical parasitic elements (out of thousands, millions, or billions) responsible for bottlenecks, choke points and weak areas.
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