dotclock100 vs 150 in ./isework/nexys4.prj

[Pierluigi Rolando]

Hi everyone,

I've received my Nexys4 DDR a few days back and I'm trying to build the project. I've checked out the px100mhz branch, and I've been compiling according to instructions, including some of the errata I've found here on this forum.

I've noticed that the nexys4.prj imports dotclock150 stuff, but then the compilation fails with this error:

==> 20180227_12:50:28 Starting: xst, see isework/nexys4.syr

xst -intstyle ise -ifn isework/nexys4.xst -ofn isework/nexys4.syr

Makefile:453: recipe for target 'isework/nexys4.ngc' failed

If I go look at the logs, it says that it needs the dotclock100 module. I'm trying to rebuild with it (by replacing 150 with 100 in the .prj). Given that it'll take a few hours, I wanted to check with you all that it's the right change to make -- I'm no VHDL expert.

Thanks,

Pierluigi

[Paul Gardner-Stephen]

Hello,

That sounds about right.  I'll aim to verify here.

Paul.

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[Pierluigi Rolando]

Ok, that fixed the dotclock issue.

The next two errors I get are:

ERROR:HDLCompiler:1314 - "/home/lanugo/mega65/mega65-core/src/vhdl/nexys4.vhdl" Line 381: Formal port/generic <iec_atn> is not declared in <machine>

ERROR:HDLCompiler:432 - "/home/lanugo/mega65/mega65-core/src/vhdl/nexys4.vhdl" Line 328: Formal <cpu_exrom> has no actual or default value.

These seem a bit less immediate to fix unless I go look at what they actually mean :-D

Will try to do another round but since it takes forever to build the VHDL I would appreciate any tips.

Thanks,

- P

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[Paul Gardner-Stephen]

Hello,

Pull px100mhz branch down again -- I believe I have fixed those there.

Paul.

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[Pierluigi Rolando]

I'll try but I only see a new commit fixing the dotclock problem for now...

Thanks,

- P

[Pierluigi Rolando]

Ok I just got the other commits -- I'm recompiling! Thanks!

- P

[Paul Gardner-Stephen]

Hello,

Check if you got the absolute latest commit, as I just found and fixed another problem.

You want 63611c0*.

Paul.

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[Pierluigi Rolando]

Hi Paul,

That fails like this:

Parsing architecture <Behavioral> of entity <container>.

ERROR:HDLCompiler:432 - "/home/lanugo/mega65/mega65-core/src/vhdl/mega65r1.vhdl" Line 261: Formal <reset> has no actual or default value.

INFO:HDLCompiler:1408 - "/home/lanugo/mega65/mega65-core/ipcore_dir/dotclock100.vhd" Line 93. reset is declared here

ERROR:HDLCompiler:854 - "/home/lanugo/mega65/mega65-core/src/vhdl/mega65r1.vhdl" Line 179: Unit <behavioral> ignored due to previous errors.

VHDL file /home/lanugo/mega65/mega65-core/src/vhdl/mega65r1.vhdl ignored due to errors

Will try if I can figure out the reset business.

[Paul Gardner-Stephen]

Which commit did you build from? I am working on some other bits and pieces on that branch at the moment, so there may be some transient problems like this.

I have already pushed a couple of commits that should fix this, and am doing a test synthesis for a related target at the moment.

Paul.

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[Pierluigi Rolando]

I've tried again with the commit you suggested (63611c0), it goes a long long way, then it fails with this error:

Annotating constraints to design from ucf file "./src/vhdl/lcd4ddr.ucf" ...

Resolving constraint associations...

Checking Constraint Associations...

ERROR:ConstraintSystem:59 - Constraint <NET "jc<9>"          LOC=J4 |>

   [./src/vhdl/lcd4ddr.ucf(276)]: NET "jc<9>" not found.  Please verify that:

   1. The specified design element actually exists in the original design.

   2. The specified object is spelled correctly in the constraint source file.

WARNING:ConstraintSystem - A target design object for the Locate constraint

   '<NET "jc<9>"          LOC=J4 |> [./src/vhdl/lcd4ddr.ucf(276)]' could not be

   found and so the Locate constraint will be removed.

ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD=LVCMOS33;>

   [./src/vhdl/lcd4ddr.ucf(276)]: NET "jc<9>" not found.  Please verify that:

   1. The specified design element actually exists in the original design.

   2. The specified object is spelled correctly in the constraint source file.

ERROR:ConstraintSystem:59 - Constraint <NET "jc<10>"         LOC=E6 |>

   [./src/vhdl/lcd4ddr.ucf(277)]: NET "jc<10>" not found.  Please verify that:

   1. The specified design element actually exists in the original design.

   2. The specified object is spelled correctly in the constraint source file.

WARNING:ConstraintSystem - A target design object for the Locate constraint

   '<NET "jc<10>"         LOC=E6 |> [./src/vhdl/lcd4ddr.ucf(277)]' could not be

   found and so the Locate constraint will be removed.

ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD=LVCMOS33;>

   [./src/vhdl/lcd4ddr.ucf(277)]: NET "jc<10>" not found.  Please verify that:

   1. The specified design element actually exists in the original design.

   2. The specified object is spelled correctly in the constraint source file.

while doing isework/lcd4ddr.ngd

I remember you changing some of the jc stuff in other commits, I'll try with something newer to see if it fixed this.

BTW, is there a way I can speed up the build a bit? I have a new-ish computer yet it still takes many hours to get to this point :-)

Thanks,

- P

[Paul Gardner-Stephen]

Hello,

If you can speed up FPGA synthesis by 10x, I suspect you would have a billion dollar business on your hands.

Which exact target do you want to build for? If it is a nexys4 ddr board, just use:

make bin/nexys4ddr.bit

That said,  the latest commits should build fine for the lcd4ddr.bit target as well.

Paul.

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[Pierluigi Rolando]

Have I been building all targets every time? Why yes, I have :-( That explains the slowness.

- P

[Paul Gardner-Stephen]

A single target should take 45 min - 4 hours with a decent fast computer, depending on phase of moon.

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[Pierluigi Rolando]

Ok the build worked! After a week of not really knowing what I'm doing I feel rather stoked :-D

[Paul Gardner-Stephen]

:) Now use that stoked feeling to full 8-bits of effect!

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