purpose of instruction sequence 0xf3, 0xc3

[dhoke]

What purpose does the (INTEL x86) instruction sequence bytes 0xf3, 0xc3, or
"REPZ ret", serve or accomplish?

Background:

In the course of debugging something, I encountered the following
instruction stream, apparently in rtl100:

51F23BCB 90 nop
rtl100.@System@@GetMem$qqri:
51F23BCC 85C0 test eax,eax
51F23BCE 7E13 jle $51f23be3
51F23BD0 FF1574C7F951 call dword ptr [$51f9c774]
51F23BD6 85C0 test eax,eax
51F23BD8 7402 jz $51f23bdc
51F23BDA F3C3 rep ret
51F23BDC B001 mov al,$01
51F23BDE E941020000 jmp $51f23e24
51F23BE3 31C0 xor eax,eax
51F23BE5 F3C3 rep ret
51F23BE7 90 nop
rtl100.@System@@FreeMem$qqrpv:
51F23BE8 85C0 test eax,eax

It appears that the instruction stream is intended, and generated from the
following source code segment from System.pas:
TEST EAX,EAX
JLE @@negativeorzerosize
CALL MemoryManager.GetMem
TEST EAX,EAX
JZ @@getmemerror
DB $F3
RET
@@getmemerror:
MOV AL,reOutOfMemory
JMP Error
@@negativeorzerosize:
XOR EAX, EAX
DB $F3

[Bruce Salzman]

"dhoke" <dhoke....@east-shore.com> wrote in message
news:48763262$1...@newsgroups.borland.com...

> What purpose does the (INTEL x86) instruction sequence bytes 0xf3, 0xc3, or
> "REPZ ret", serve or accomplish?
>

I believe it is a speed optimization that has to do with the pre-fetch cache.

--
Bruce

[lixan]

AMD x86-64 processors cannot predict single-byte near RET instructions
when they are either the target of a branch or immediately preceded by a
conditional branch. (See section 6.2 in the Athlon 64/Opteron
optimization guide)

AMD's recommended solution is to either reorder instructions so that
this situation does not occur, or use the REP prefix on the RET
instruction.PS Before ask question try google first.